Cadence Design Systems, Inc. (NASDAQ: CDNS) and Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) today announced that Cadence® is providing key capabilities to TSMC Reference Flow 8.0. The new reference flow addresses design challenges at 45 nanometers, providing statistical timing analysis for intra-die variation, automated DFM hot-spot fixing and new dynamic low-power design methodologies.
Reference Flow 8.0 is the latest generation of TSMC's design methodology that increases yields, lowers risks and improves design margins. The flow provides a reference of qualified design building blocks that give designers a proven path from specification to tapeout.
"TSMC and Cadence are continuing an established track record of innovation with our inclusion in Reference Flow 8.0," said Eric Filseth, corporate vice president of Marketing at Cadence. "TSMC's Reference Flow 8.0 is a complete, integrated and comprehensive solution for 45-nanometer design. The breadth of offerings and easy-to-use flow are the key values that Cadence delivers to our mutual customers."
"We worked closely with Cadence to address the complex issues that face designers at 45 nanometers," said Kuo Wu, director of EDA and IP Marketing at TSMC. "Through our ongoing collaboration with Cadence, we're able to provide designers with new power management, variation-aware analysis, and design for manufacturing technologies, all tightly integrated into TSMC Reference Flow 8.0 and targeted to TSMC's 45-nanometer process."
The silicon-proven TSMC Reference Flow 8.0 allows designers to accelerate advanced 45-nanometer design with lower power, faster cycle time, higher quality and lower manufacturing risk. The Cadence contribution within TSMC Reference Flow 8.0 is based on several new capabilities in the Cadence Encounter® digital IC design platform and the Cadence Logic Design Team Solution. The new capabilities are supported by a broad range of Cadence tools, including Incisive® Design Team Simulator, Incisive Enterprise Simulator and the Cadence SoC Encounter GXL™ RTL-to-GDS system which incorporates:
Encounter RTL CompilerEncounter Conformal® technologiesCadence Encounter TestCadence NanoRoute™ nanometer routerCadence Encounter Timing SystemCadence VoltageStorm® power analysisCadence QRC extractionCadence CMP PredictorCadence Chip Optimizer.
Part of a longstanding and ongoing collaboration between TSMC and Cadence, Reference Flow 8.0 delivers an RTL-to-GDS design flow that accelerates time to volume for high-performance and low-power designs. The flow delivers a comprehensive methodology to address complex design issues at 45 nanometers by providing advanced design techniques to manage power consumption, addressing tighter manufacturing parameters, tackling an exponential increase in power leakage, and meeting new extraction requirements to accurately predict the silicon behavior of an IC's interconnect, and also to account for process variability at 45-nanometer process node.
These capabilities, described in the order of RTL-to-GDS, include support for the Si2 Common Power Format (CPF)-compliant low-power flow covering design, verification, implementation and analysis. The low-power flow enables new leakage-power reduction strategies such as Power Shut Off (PSO), which requires not only synthesis and physical design support, but also functional and implementation verification capabilities that are unique to the Cadence Logic Design Team Solution. Enhanced support for the new 45-nanometer routing rules and yield-optimized routing are part of the key solutions for 45-nanometer process technology.
In the analysis category, process-variation extractions, thermal analysis and thermal-aware leakage analysis address new dimensions of design careabouts. Cadence advanced variation-aware analysis tools for next-phase SSTA capabilities, which now also include statistical leakage analysis and optimization, improve the awareness of manufacturing effects.
To further improve design yield, TSMC Reference Flow 8.0 helps prevent, detect and correct for yield limiters, as well as improve process windows and manage variations. The Cadence Chip Optimizer, together with Encounter NanoRoute provides defect-based yield optimization, including thickness variability prediction capabilities from Cadence CMP Predictor for model-based intelligent metal fill and CMP hotspot detection/correction. The CMP Predictor can be used with Cadence QRC Extraction to account for thickness variations in extraction and timing analysis with Encounter Timing System. Additionally, the reference flow provides for lithography-aware routing and an interface to third-party lithography analysis tools for lithography hot-spot detection and automated hot-spot correction with the Cadence SoC Encounter system.
Finally, the 45-nanometer-aware design for test (DFT) features, such as power-aware ATPG, XOR compression and at-speed diagnostic completes the Cadence solution highlights. This reference flow supports designs targeting TSMC's 45-nanometer process technologies.
As a supporting element to TSMC Reference Flow 8.0, Cadence also provides entire CPF compliance 45-nanometer low-power tutorials and test cases, covering simulation, design, implementation and analysis, based on the TSMC reference flow. Customers can use these tutorials and test cases to observe the complete flow in action using an actual design.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company's total managed capacity in 2006 exceeded seven million (8-inch equivalent) wafers, including capacity from two advanced 12-inch GigaFabs, four eight-inch fabs, one six-inch fab, as well as TSMC's wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.