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Cadence and Denali Team Up to Enable Advanced DDR-PHY Methodology
Industry's Most Advanced DDR-PHY Solutions Achieved With Denali's Databahn PHY Architecture and CPF-Enabled Cadence SoC Encounter and Encounter Timing System

SAN JOSE Calif., 31 May 2007

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, and Denali Software, a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that they have delivered an advanced DDR-PHY implementation methodology based on the Cadence® Encounter® digital IC design platform. This new methodology uses Cadence SoC Encounter™ RTL-to-GSDII system for design and physical implementation and Cadence Encounter Timing System for design closure and final timing, signal integrity and signoff—both are key technologies of the CPF-enabled Encounter platform.

Using the combination of Denali's Databahn DDR controller and PHY IP with the Encounter technologies, customers can now achieve DDR memory-system implementations at 65 nanometers and at speeds exceeding 400 MHz.

"DDR-PHY implementation had become one of the top problems for our customers," said Brian Gardner, vice president of IP products at Denali. "When we set out to solve this problem, we quickly realized the need for high-quality tools that provide a consistent view of timing, signal integrity, and power throughout the design and physical implementation process. Using SoC Encounter and Encounter Timing System, we were able to put together a complete system solution for DDR-PHY development that enables customers to achieve higher-quality designs, in less time, and with minimized risk. Cadence was the obvious choice for selecting a partner to solve this problem."

This methodology combines innovative design techniques, and world-class implementation and analysis solutions enabling robust customer design kits, or complete IP hardening leading to the market's smallest and highest performance configurable DDR-PHY products. An estimated 70 percent of new SoC designs use DDR-memory-subsystem IP. DDR memory systems with superior system-performance requirements have become a critical factor for products in the networking, computing, and consumer-electronics segments where memory bandwidth is a critical factor for achieving system performance.

Additionally, due to dramatic increase in clock speeds and the storied challenges of 65-nanometer implementation, the ability to implement DDR-PHYs and quick closure on timing has become a serious bottleneck to time to market. Some of the world's largest IDMs have declared this as their number one problem. After careful evaluation, Denali has standardized on SoC Encounter and Encounter Timing System for superior DDR-PHY design, physical implementation, timing closure, and signoff analysis. With this solution, Denali now delivers proven design kits, methodology services, and hardened IP to their customers.

"We are very pleased to be working with Denali, a recognized leader in memory systems and IP that are deployed in a wide scope of end applications ranging from mobile phones to world-class routers," said Dr. Chi-Ping Hsu, corporate vice president, IC Digital and Power Forward at Cadence. "The Denali DDR controller and PHY IP represent an optimal solution that offers a wide range of programmability and configurability. The Cadence Encounter platform together with Si2's CPF and the Denali DDR-PHY methodology provides a uniquely powerful and flexible solution that comprehensively addresses power, performance, and time-to-market challenges of today's SoC designs."

A Web cast providing a more comprehensive overview, highlighting the benefits of this joint methodology, can be viewed now at: www.denali.com/webcast/socencounter.

About Denali
Denali SreferenceInc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND and DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com.

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence® software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:
Michael Fournell
direct:408.428.5135
fournell@cadence.com
Cadence Design Systems, Inc.
Pierre Golde
direct:650.461.7262
pgolde@denali.com
Denali Software, Inc.


Cadence and Encounter are registered trademarks, and SoC Encounter and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the U.S. and other countries.

Denali and the Denali logo are registered trademarks, and Databahn is a trademark of Denali Software, Inc. All other trademarks are the property of their respective owners.