Media Alert: Cadence Design Systems, Inc. Announces Line-Up of Events for the Design Automation Conference (DAC) in San Diego
SAN JOSE, CA, 23 May 2007

Join Cadence and partners at presentations and informative breakfast and lunch panels listed below.

Monday, June 4, 12:15 pm - 12:45 pm
San Diego Convention Center, Room 8
Presentation of Marie R. Pistilli Women in EDA Achievement Award
Women have made important contributions and strides in the EDA industry for over 20 years. To recognize those who have dedicated time towards these achievements, the DAC Executive Committee presents an annual award to honor an individual who has made significant contributions in helping women advance in the field of EDA technology. This year’s winner is Jan Willis, senior vice president, Industry Alliances at Cadence.

Monday, June 4, 3:30 pm – 4:30 pm
San Diego Convention Center, Cadence Booth #2753
Presentation on Cadence in the Automotive Market Segment
Ted Vucurevich, senior vice president and chief technology officer at Cadence, discusses the company’s pragmatic and thoughtful approach to the Automotive Market Segment and its unique needs. Based on a strong history in automotive semiconductor applications and with strengths in AMS design, functional verification, services and partnerships, Cadence continues to provide the capabilities that automotive customers require from silicon to systems level.

Tuesday, June 5, 7:30 am - 9:00 am
San Diego Convention Center, Rooms 30CDE
Breakfast provided
Cadence and Arm Wireless Technical User Group Meeting
Hear about real-world examples of successful ARM and Cadence technologies deployed for wireless applications.

Tuesday, June 5, 10:15 am - 11:00 am
San Diego Convention Center, Pavilion
Panel on Career Advancement for Technologists: An Interview with the Marie R. Pistilli Women in EDA Achievement Award Winner
Jan Willis, this year’s award winner, is senior vice president, Industry Alliances at Cadence. She will offer her advice on what pays off and what doesn’t – and the skills that mid-career technologists need to advance their careers. The moderator is William H. Joyner, Jr., of IBM Corp.

Tuesday, June 5, 11:30 am - 1:00 pm
San Diego Convention Center, Rooms 30CDE
Lunch provided
Panel on Productivity Improvement and Risk Reduction in Low-Power Design
In one short year, tremendous progress has been made in delivering a holistic low-power design flow and in developing broad ecosystem support for that flow across the industry. Join Cadence, other industry leaders, and users who will share their low-power design experiences using the Cadence® Low-Power Solution.

Wednesday, June 6, 11:30 am - 1:00 pm
San Diego Convention Center, Rooms 30CDE
Lunch provided
Panel on SystemVerilog Design with Verification: Oil and Water Can Mix
The traditional view is that logic designers design and verification engineers verify. However, the reality is that today's accelerated project schedules require bugs to be found as early as possible. Thus, certain aspects of verification are essential as part of the design process. This session describes Design with Verification, in which logic designers can leverage formal analysis and more sophisticated test benches at the block level, and its links to full-chip verification. Various experts will discuss how SystemVerilog, as an integrated design and verification language with support for assertions, constraints, coverage, and more verifiable RTL, is enabling easy adoption of Design with Verification.

Thursday, June 7, 7:30 am - 9:00 am
San Diego Convention Center, Rooms 30CDE
Breakfast provided
Seminar hosted jointly by IBM and Cadence: Optimizing the Path into ASIC for First-Time-Right Silicon
ASIC designers and customers who are currently doing or planning high-performance designs at 65 or 45 nanometers should attend this seminar. Attendees will hear from both IBM and Cadence about an optimized methodology to accelerate the path to success for customers’ ASIC designs with IBM. Speakers will present front-end design methodology for 65-nanometer ASIC design that has been optimized to work with the IBM ASIC flow. They will also discuss key power management techniques designers can use to reduce power consumption in high-performance designs. IBM will present their ASIC roadmap for 65- and 45-nanometer technologies.

For more information, please contact:
Michael Fournell
direct:408.428.5135
fournell@cadence.com
Senior Public Relations Manager
Cadence Design Systems, Inc.