Unisys Improves Logic Design Team Productivity With Cadence Incisive Formal VerifierCiting Increased Productivity, Unisys Incorporates Assertion-Based Verification Methodology into Its Production Design FlowSAN JOSE, Calif., 30 Apr 2007
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced that Unisys Corporation has incorporated Cadence® Incisive® Formal Verifier into its design flow for assertion-based formal analysis. Using Formal Verifier, Unisys experienced productivity gains and improvements in overall quality, delivering advanced complex chips at multiple sites.
Part of the Cadence Logic Design Team Solution's "Design with Verification" approach, Formal Verifier exposed many hard-to-find functional bugs early in the Unisys design cycle, enabling greater team productivity and accelerating project completion. Logic Designers were able to verify design blocks months prior to testbench simulation, resulting in faster and more cost-efficient overall chip verification. Moreover, the assertions developed by the team early in the design cycle were fully reusable in simulation and acceleration/emulation later in the flow, adding greater observability and leading to faster debug and an overall shorter verification cycle.
"Design with verification starting with Incisive Formal Verifier has helped us take our enterprise servers to market more efficiently and earlier, and at a lower cost," said Steve Guarrieri, vice president of platform development at Unisys. "In addition, it helped mitigate the risk of corner-case re-spins, and we've found it easy to broadly deploy into our standard product flow across multiple projects, including our most advanced and complex ASICs."
The Unisys team reported success on multiple projects, including a highly complex ASIC design. The ease of adoption and designer-friendly nature of the Formal Verifier technology further enhanced the Unisys verification environment that included Incisive Design Team Simulator and Incisive Palladium® Emulator. When combined with the comprehensive Plan-to-Closure assertion-based verification methodology, Unisys realized significant productivity gains.
"We are excited to see companies such as Unisys, reaping savings and benefits from the Cadence Logic Design Team Solution's early verification technology," said Steve Glaser, corporate vice president of marketing, Verification Division at Cadence. "Incisive Formal Verifier offers a complete plan-to-closure assertion-based verification methodology, yields tremendous productivity and quality gains, and provides a perfect fit for design teams that want to optimize RTL bring-up and improve overall project time to market."
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Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com