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Hitachi Communication Technologies Speeds Time to Market for ASIC Designs with Cadence Synthesis
Encounter RTL Compiler Improves Time to Quality on Six 130-Nanometer ASIC Tapeouts by Reducing Synthesis Turnaround Times by Up To 70%

SAN JOSE, Calif., 27 Mar 2006

Cadence Design Systems, Inc. (NASDAQ:CDNS) today announced that Hitachi Communication Technologies, Ltd. has improved synthesis turnaround time by 50 to 70 percent with Cadence® Encounter® RTL Compiler global synthesis. Encounter RTL Compiler, a key technology of the Encounter digital IC design platform, helped Hitachi Communication Technologies to achieve faster time to market on six 130-nanometer ASIC designs.

Hitachi Communication Technologies is a leader in the design, development and worldwide sales of information and communication system-related products, featuring optical access, broadband mobile and IP networks. The six ASICs that the company taped out with Encounter RTL Compiler synthesis were a combination of wireline and wireless communications chips. A long-time user of Cadence technology, Hitachi Communication Technologies initially adopted Encounter RTL Compiler synthesis because of its ability to reduce chip area. This latest achievement stands to expand the company's commitment to Cadence Encounter synthesis even further.

"We adopted Encounter RTL Compiler synthesis because it helped us to reduce area by an average of 25%. The faster synthesis turnaround time that Encounter RTL Compiler delivered enabled us to spend more time focusing on verifying last-minute modifications of the design specification," said Hideya Sato, CAD department manager in the Carrier Network Systems Division at Hitachi Communication Technologies. "Cadence Encounter RTL Compiler synthesis has proven to be a complete synthesis solution that delivers us benefits over our existing solution, and we are considering adopting it as the standard synthesis tool throughout the company."

Encounter RTL Compiler global synthesis has proven through tapeouts to deliver improved performance, smaller die sizes, lower power consumption, and faster design closure through place and route. Cadence defines the combination of these metrics as quality of silicon (QoS). Encounter RTL Compiler is available in L, XL, and GXL configurations in conjunction with Cadence's segmentation strategy.

"We are excited that our global synthesis technology helped improve time to quality for Hitachi Communication Technologies on these six tapeouts," said Dr. Chi-Ping Hsu, corporate vice president at Cadence. "Encounter RTL Compiler synthesis is a production-proven tool that delivers real business benefits."

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics systems. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:
Judy Erkanat
direct:408.894.2302
jerkanat@cadence.com
Cadence Design Systems, Inc.


Cadence, Encounter and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.