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Cadence Delivers High-Performance, Low-Power Design IP Supporting LPDDR3 Memory Standard
New Cadence Controller and PHY IP Solution Supports Latest Version of Memory Interface For Smartphone and Tablet Applications

SAN JOSE, Calif., 21 Mar 2012

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced the addition of design intellectual property (IP) for the LPDDR3 mobile memory standard to the company’s design IP portfolio. Designed to provide the high bandwidth and low power consumption required by smartphones and tablets, the Cadence LPDDR3 memory IP solution includes integrated controller and PHY support, virtual prototyping, verification IP and Allegro® design-in kits to accelerate implementation and reduce design risk. Cadence's highly configurable design IP allows the LPDDR3 standard to be combined with others in a single controller and PHY to enable SoCs that support multiple memory standards, making one design usable by multiple markets.

“To keep pace with the growing processing capabilities of today’s smartphones and tablets, SoC designers must support memory standards that are evolving just as quickly,” said Marc Greenberg, director of product marketing, SoC Realization Group, Cadence. “At Cadence, our goal is to enable early access to these standards by offering customers a broad range of high-performance, low power design IP standards, like LPDDR3, so they can quickly integrate the standard into new SoC designs.”

As part of the LPDDR3 launch, Cadence has upgraded the bandwidth management engine, Placement Queue 2.2, to optimize the way memory is accessed to improve overall system performance and power consumption.

In addition to LPDDR3, Cadence offers IP for other mobile and non-mobile memory standards in high demand by SoC designers, including Wide I/O and DDR4. More information about the Cadence verification IP catalog and the Allegro Design-in kits is available on the Cadence web site.

About LPDDR3
The LPDDR3 standard will offer an extension to the bandwidth of LPDDR2, reaching 6.4GByte/s per die (1600MT/s per pin) and allowing 12.8GByte/s for a dual channel configuration. It will support both PoP and discrete packaging types, allowing versatile usage. LPDDR3 will preserve the power-efficient features of LPDDR2, allowing for fast clock stop/start, low-power self-refresh, and smart array management. For more information about LPDDR3, please visit JEDEC, the microelectronics industry’s open standards organization.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:
Bob Nelson
Cadence Design Systems, Inc.
408-201-2402
nelson@cadence.com


Cadence, Allegro and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.