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MEDIA ALERT: Cadence to Keynote, Present Papers at ISQED
JOSE Calif., 19 Mar 2012

Tom Beckley, senior vice president of Research and Development, Custom IC and Signoff, Silicon Realization Group at Cadence Design Systems, Inc, (NASDAQ: CDNS), will deliver a keynote on advanced node chip design at the International Symposium on Quality Electronic Design (ISQED). In addition, Cadence engineers will participate in two paper presentations at the conference.

WHEN:
March 19 to March 21

WHERE:
Techmart Center, Santa Clara, Calif.

WHAT:
Beckley, who leads R&D for Cadence custom IC and signoff technology, will deliver a keynote on, “Taming the Challenges in Advanced Node Design” at 8:15 a.m. March 20.

At 2:30 p.m. March 20, Cadence will join representatives of the IBM Semiconductor Research and Development Center to deliver a paper titled, “Understanding, Modeling, and Detecting Pooling Hotspots in Copper CMP.”

At 5:30 p.m. March 20, Sachin Shrivastava and Harindranath Parameswaran from Cadence will deliver a paper titled, “Efficient Reduction Techniques for Statistical Model Generation of Standard Cells.”

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:
Dean Solov
Cadence Design Systems
408.944.7226
dsolov@cadence.com


Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc., in the United States and other countries. All other marks and names are the property of their respective owners