Cadence Design Systems, Inc. (NYSE: CDN) announced that Procket Networks, a leading provider of high performance Internet Protocol (IP) routers, has successfully used the Cadence® Encounter RTL Compiler synthesis tool to tape out six high-end networking chips. The networking processors contain up to 250 million transistors per chip and run at variable speeds exceeding 400MHz. Procket chose to standardize on Encounter RTL Compiler as its synthesis tool of choice to increase overall chip speed in its system-on-chip (SoC) designs. The wire-centric methodology used in Encounter RTL Compiler synthesis enables the Encounter Digital IC Platform to provide a fast route to silicon by enabling faster performance and reductions in area and power.
"In the middle of our project, we were able to integrate RTL Compiler into our production environment for all six chips, while meeting all of our demanding schedule dates. This was possible because of great runtimes, better quality of silicon, as well as compatibility with our existing implementation tools and methodology," said Jeff Purnell, vice president of engineering for Procket. "The roadmap for RTL Compiler technology and support from Cadence continues to improve with each new generation. We have been extremely satisfied using the tool thus far and plan to continue using Encounter RTL Compiler as our synthesis tool for the next generation of designs."
The new generation technology behind Encounter RTL Compiler enables Procket to use the synthesis tool for designing high-speed, large nanometer-scale chips. Used throughout the silicon design chain by application-specific integrated circuit (ASIC) designers, intellectual property (IP) vendors, integrated circuit (IC) and fully programmable custom VLSI designers such as Procket, the Encounter RTL Compiler tool works to increase overall chip speed, reduce turnaround time, and help customers achieve a high quality of silicon.
"Only Encounter RTL Compiler provides the runtime and capacity that companies like Procket need to handle multi-million transistor wire-centric designs," said Chi-Ping Hsu, general manager of Encounter synthesis, Cadence Design Systems, Inc. "But more importantly, we provide the utmost in quality of silicon, enabling our customers to get to market faster with differentiated products."
Quality of Silicon
In nanometer design, every aspect of a chip becomes dominated by interconnect-related parameters, design rules, and failure mechanisms. In order to truly understand the physical properties of a design at 130nm and below, a new, meaningful metric for speed, area, power, and test must be applied. Quality of silicon is the new generation metric that measures performance, area, and power after wires.
Encounter RTL Compiler synthesis uses a unique set of global focus synthesis technologies that offer chip designers the highest quality of silicon in less time and with less effort, while still being backward compatible with traditional synthesis tools.
About Cadence Design Systems, Inc.
Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 4,800 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.