Fujitsu Successfully Completes 66 Consecutive Designs with Cadence EncounterCadence Encounter-Based Reference Design Flow Delivers First-Pass Silicon in JapanYokohama, Japan/San Jose, CA, 25 Jan 2005
Cadence Design Systems, Inc. (NYSE: CDN) (Nasdaq: CDN) today announced that Cadence has helped Fujitsu to successfully achieve first-pass silicon on 66 consecutive designs. The designs were enabled by a standardized reference design flow based on Cadence® Encounter IC implementation technology.
Leveraging the benefits of its global Premier Design Partner agreement with Cadence, Fujitsu developed a reference flow based on the Encounter digital IC design platform. This reference flow has been broadly deployed at Fujitsu's worldwide design centers and by their COT partners. The designs were at 90 and 130 nanometers. All were developed on Fujitsu's world-class advanced process technologies.
Included among the 90 nanometer designs was a design for high-end cellular phones with an extremely strict low-power specification. Fujitsu's low power process technologies utilizing copper wires and low-k dielectrics, and Encounter's low-power solutions helped Fujitsu reduce power consumption by 83 percent. This greatly enhanced Fujitsu's position as a leading low-power chip supplier for the cellular phone series.
"We are extremely pleased that our global collaboration with Cadence has produced such tremendous success so quickly," said Kazuyuki Kawauchi, executive vice president of Fujitsu Microelectronics America Inc. "We are working with Cadence in other areas, and I'm confident that we will see many further tangible achievements coming up over the next few years."
"Fujitsu's ability to achieve 66 first-pass silicon successes in such a short period of time is a direct result of the PDP agreement we signed with this important customer last year," said Ryoichi Kawashima, president, Cadence Japan. "I am very pleased with this milestone in the progress of our ongoing commitment to our customers' success."
"Fujitsu is known as one of the most successful semiconductor vendors at the 90-nanometer process node," said Wei-Jin Dai, platform vice president, digital IC implementation at Cadence. "It is our pleasure to announce that the advantages of Cadence Encounter products on signal-integrity-based timing closure and low power were proven on Fujitsu's leading-edge process technologies. We sincerely appreciate all of Fujitsu's efforts in maximizing the benefits of Encounter."
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Cadence is the world's largest supplier of electronic design technologies and engineering services. Cadence products and services are used to accelerate and manage the design of semiconductors, computer systems, networking equipment, telecommunications equipment, consumer electronics, and other electronics based products. With approximately 4,850 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and trades on both the New York Stock Exchange and Nasdaq under the symbol CDN. More information is available at www.cadence.com