will be under system maintenance from Tuesday June 28, 6pm PT to Sunday July 3, 11pm PT. Login and registration will be disabled.


VeriSilicon Tapes out Flip-Chip Design With Cadence Encounter
Cadence Encounter Digital IC Design Platform Enables Automatic Flip Chip Flow for 1.6M Gate SoC

SAN JOSE, Calif., 23 Jan 2006

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that VeriSilicon Holdings Co., Ltd. (VeriSilicon), a leading ASIC design foundry, has successfully taped out a complex, high-speed, flip-chip SoC using an automatic flip-chip flow based on the Cadence® Encounter® digital IC design platform. VeriSilicon achieved first silicon success on the SoC, which is in volume production.

With SoC Encounter, VeriSilicon reduced the chip's die size, increased performance, improved timing optimization, and achieved better power integration. These benefits provided important advantages on the flip-chip design, which has a die size of 8.4x8.4mm2, 1.6 million gates, and 6 main clocks running at 250MHz. The design's packaging is a BGA729 Flip Chip, based on the SMIC 0.15um LV 1P7M process.

"As an ASIC design foundry, VeriSilicon is consistently looking for ways to improve the design flow to better serve customers. The greatest challenge in implementing a flip-chip SoC lies in the automatic flip-chip flow, such as automatic bump assignment and RDL routing," said Nianfeng Li, vice president of design methodologies at VeriSilicon. "The Cadence SoC Encounter system works smoothly on top of the VeriSilicon Standard Design Platform (SDP) and our special I/Os, and its advanced features helped us greatly speed up the flip chip design process."

The Cadence SoC Encounter system helped VeriSilicon in IO pad optimization based on bump location and assignment, bump re-assignment based on pad location, automatic RDL routing with user-specified constraints, and multiple routing widths. It also automatically connected power cells to bumps, and used verification support with verify commands and automatic bump placement. Encounter QRC was used for manufacturing-aware parasitic extraction, while VoltageStorm® was used for power analysis.

"We are very happy that VeriSilicon chose the Cadence Encounter design flow to develop this flip-chip SoC," said Wei-Jin Dai, corporate vice president at Cadence. "Automatic bump assignment and RDL routing reduced the overall schedule time, while delivering a significantly improved Quality of Silicon (QoS) for this design. Encounter's integrated design flow was an important factor in reducing time-to-market."

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

For more information, please contact:
Judy Erkanat
Cadence Design Systems, Inc.
Peggy Ng
Cadence Design Systems Asia Ltd.

Cadence, Encounter and the Cadence logo are registered trademarks and SoC Encounter is a trademark of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.