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December

16 Dec 2009 Cadence Announces IIT Delhi as Winner of Annual Design Contest14 Dec 2009 Zoran Deploys Cadence Virtuoso Software for Complex, Advanced Technology, Mixed-Signal Chip14 Dec 2009 Fairchild Semiconductor Selects Cadence as Primary EDA Partner10 Dec 2009 Cosmic Circuits Adopts Cadence Virtuoso 6.1 for Complex Analog and Mixed-Signal Designs08 Dec 2009 AppliedMicro Standardizes on Cadence Encounter Digital Implementation System07 Dec 2009 Cadence Strengthens Virtuoso Custom IC Design Leadership
 
November

25 Nov 2009 IC Plus Standardizes Verification Process with Cadence Incisive Solution16 Nov 2009 Cadence Announces Expanded SoC Design Alliance with Toshiba Corporation04 Nov 2009 Exar Selects Cadence as Mixed-Signal EDA Provider03 Nov 2009 Cadence Marks Annual Innovation Day with Honors for its Top Technology Leaders02 Nov 2009 Hitachi Achieves Test Compression Levels Four Years Ahead of Industry (ITRS) Roadmap by Leveraging Cadence OPMISR Compression Technology
 
October

29 Oct 2009 SMIC and Cadence Announce the Availability of 65-Nanometer Low power Reference Flow 4.028 Oct 2009 Cadence Reports Q3 2009 Financial Results27 Oct 2009 IC Package Designers Boost Productivity with New Cadence Allegro SiP and IC Packaging Software27 Oct 2009 Cadence Leverages New Miniaturization Capabilities to Advance PCB Design Leadership27 Oct 2009 Silicon Hive Utilizes Cadence Palladium III Solution for Highest Quality IP for Multi-Core Multi-Million Gate Designs22 Oct 2009 Cadence Design Systems to Host Mixed-Signal Design Summit20 Oct 2009 SMIC Adopts Cadence DFM Solutions for 65- and 45-Nanometer IP/Library Development and Full Chip Production19 Oct 2009 Cadence and ARM Fabric Collaborate to Increase Engineer Productivity and Drive Down Time to Market for SoC Integration19 Oct 2009 STARC and Cadence Collaborate to Develop Next-Generation Analog/Mixed-Signal Reference Flow15 Oct 2009 Cadence Design Systems to Host Second Annual Silicon Valley Power Forward Low-Power Design Summit13 Oct 2009 Cadence Incisive Verification Management Solution Enables Fujitsu Microelectronics Solutions to Achieve Aggressive Verification Goals12 Oct 2009 SHHIC Adopts Broad Range of Cadence Solutions for Advanced Semiconductor Design09 Oct 2009 Cadence Announces Third Quarter 2009 Financial Results Webcast06 Oct 2009 Cadence Extends Its TLM-Driven Design and Verification Solution to Support Leading Embedded Software Environments05 Oct 2009 Cadence Introduces Incisive Enterprise Verifier, Delivering Dual Power of Formal Analysis and Simulation Engines05 Oct 2009 Cadence Enables Early Validation of Next-Gen 4G/LTE Wireless Designs with Rohde & Schwarz T&M Solution01 Oct 2009 Cadence Introduces the EDA Industry’s First Verification Solution for PCI Express 3.0
 
September

29 Sep 2009 Cadence Physical Verification System Supports TSMC’s Interoperable iDRC and iLVS Formats for 40-Nanometer Design29 Sep 2009 Cadence Extends Performance Leadership with Expanded Multi-Core Support28 Sep 2009 Fuji Electric Device Achieves Significant Cost Reduction with Cadence Virtuoso Accelerated Parallel Simulator23 Sep 2009 Join Cadence at CDNLive! Silicon Valley22 Sep 2009 Linear Technology Adopts Broad Range of Cadence Mixed Signal Design Technology03 Sep 2009 Cadence Senior Vice President and Chief Financial Officer Kevin Palatnik to Present at the Deutsche Bank 2009 Technology Conference
 
August

31 Aug 2009 Cadence and GLOBALFOUNDRIES Announce Broad, Multi-Year Technology Agreement27 Aug 2009 Cadence Design Systems Appoints John Bruggeman as Chief Marketing Officer25 Aug 2009 Tilera Adopts Broad Range of Cadence Solutions for Multicore Processor Design17 Aug 2009 Cadence Low-Power Solution Selected for Global Unichip’s PowerMagic Low-Power Design Methodology03 Aug 2009 Nethra Enlists Cadence Incisive Palladium Accelerator/Emulator To Speed Development of Advanced HD Image Processor
 
July

30 Jul 2009 UMC Adopts Cadence 40-Nanometer Reference Flow for Low Power, Verification, Implementation and DFM-Aware Design29 Jul 2009 Cadence Reports Q2 2009 Financial Results29 Jul 2009 Taiwan’s Industrial Technology Research Institute Adopts Cadence C-to-Silicon Compiler to Boost Designer Productivity29 Jul 2009 Cadence Achieves First-Silicon Results on 32nm Common Platform™ Technology28 Jul 2009 Freescale Achieves Design Cycle Reduction and Superior Silicon Predictability with Cadence Model-Based Physical and Electrical DFM Solutions27 Jul 2009 Cadence Announces that STMicroelectronics Adopts Encounter Signoff Solutions for Designs from 65 to 32 Nanometers27 Jul 2009 VeriSilicon Delivers Chip Designs on Time and at Lower Cost with Cadence InCyte Chip Estimator27 Jul 2009 LG Electronics Adopts Cadence Conformal Technology for Improved Engineering Design Management, Faster Time to Market27 Jul 2009 Cadence Validates ARM Optimized Libraries for 45nm SOI Process23 Jul 2009 Cadence Delivers 28-Nanometer Design Capabilities to TSMC Reference Flow 10.023 Jul 2009 TSMC and Cadence Expand Collaboration to Deliver Advanced, Feature-Rich Process Design Kits23 Jul 2009 First OVM World Booth To Be Featured at Design Automation Conference in San Francisco22 Jul 2009 OVM World Collaborates on Accellera’s Industry Solution for VIP Interoperability22 Jul 2009 MEDIA ADVISORY: Meet at DAC with Leading IP Suppliers During ChipEstimate.com's IP Talks!15 Jul 2009 Cadence Showcases Comprehensive Design Solutions at 46th DAC15 Jul 2009 Ricoh Joins Power Forward Initiative15 Jul 2009 Cadence Announces National Semiconductor Adoption of Virtuoso Simulation Solution for Complex Analog Designs15 Jul 2009 Cadence Introduces First TLM-Driven Design and Verification Solution to Increase Engineering Productivity over RTL-based Flows14 Jul 2009 Hitachi Implements 50-Million Gate Design Using Cadence Encounter Digital Implementation System13 Jul 2009 Toshiba Information Systems (Japan) Selects Cadence Mixed-Signal Design Solution10 Jul 2009 Cadence Announces Second Quarter 2009 Financial Results Webcast08 Jul 2009 STARC Integrates Litho-Aware 45nm Design Flow using Cadence Encounter Digital Implementation System08 Jul 2009 STARC Integrates Cadence Encounter Solution for Complex, Large-Scale Designs07 Jul 2009 Fujitsu Microelectronics Solutions Adopts Cadence Verification Technology for Its Toughest Mixed-Signal Designs07 Jul 2009 Japan Aerospace Exploration Agency Adopts Cadence Virtuoso IC 6.1 and Spectre Simulator for Complex Analog and Mixed-Signal Designs
 
June

30 Jun 2009 Hitachi Achieves 40% Reduction in PCB Place-and-Route Design Time With Cadence Global Route Environment29 Jun 2009 Cadence CDNLive! EMEA User Conference Energizes the Electronics Industry29 Jun 2009 Cadence Collaborates with Toshiba Corporation on Integrated Design Environment for COT and SoC Design24 Jun 2009 Cadence and Xilinx Simplify SoC Development with Enterprise Verification Capabilities for FPGA Targeted Design Platforms17 Jun 2009 IP Talks! 2009: IP Returns to Center Stage at DAC16 Jun 2009 Kaben Wireless Silicon Achieves up to 7X Performance Boost with Cadence Virtuoso Accelerated Parallel Simulator15 Jun 2009 Taiwan’s Industrial Technology Research Institute Achieves Digital Video Tuner Tapeout Success with Cadence Virtuoso IC 6.1 15 Jun 2009 Cadence Board Member Alberto Sangiovanni-Vincentelli Honored With 2009 IEEE/RSE Wolfson James Clerk Maxwell Award12 Jun 2009 Media Alert: Power Forward Initiative presents: Power-Aware Design Summit10 Jun 2009 Cadence Announces Restructuring09 Jun 2009 Faraday Technology Reduces IC Power Consumption and Cuts Design Time by 20 Percent Using Cadence Low-Power Solution09 Jun 2009 Cadence QRC First Full Chip Extractor to be Qualified for TSMC’s Interoperable (iRCX) Format for 65 and 40 Nanometer Design08 Jun 2009 Cadence Unveils Integrated Chip Planning and Implementation Solution to Improve Predictability and Reduce Risk of IC Designs08 Jun 2009 Casio Selects Cadence C-to-Silicon Compiler for High-Level Synthesis01 Jun 2009 China's Academy of Sciences Adopts Cadence Incisive Xtreme III System to Validate Next-Generation Multi-core Processor Designs
 
May

27 May 2009 Netronome Adopts Broad Scope of Cadence Technology26 May 2009 Cadence Design Systems Presents at the RBC Technology, Media and Communications Conference20 May 2009 Cadence Senior Vice President and Chief Financial Officer Kevin Palatnik to Present at the Bank Of America Merrill Lynch Technology Conference18 May 2009 PLDA Achieves IP Success with Cadence SuperSpeed USB (USB 3.0) Verification IP18 May 2009 Cadence Encounter Digital IC Design Platform Adds 200 New Customers, including Ricoh and Siano18 May 2009 Cadence Speeds Systems Development with Automated Transaction-Level Verification18 May 2009 NXP Semiconductors Accelerates Design Cycle using New Cadence Encounter Digital Implementation System for Industry’s First 45nm Digital TV Processor18 May 2009 Cadence and Virtutech Extend Metric-Driven Verification to Virtual Systems Development18 May 2009 Cadence Introduces Innovative FPGA-PCB Co-Design Solution14 May 2009 Cadence Announces Winner of Second EMEA Student Design Contest12 May 2009 SANYO Adopts 2 Key Products from Cadence to Tackle Complex Analog and Mixed-Signal Designs12 May 2009 DiBcom Leverages Combined Cadence Low-Power and Mixed-Signal Solutions to Create Advanced Mobile TV System-on-Chip11 May 2009 BroadLight Increases Network Processor Frequency by 30 Percent using New Cadence Encounter Digital Implementation System 07 May 2009 Cadence Encounter Digital Implementation System Used by Gennum’s Snowbush IP Group to Speed Delivery of Industry’s First 45nm USB 3.0 PHY IP
 
April

30 Apr 2009 Cadence Senior Vice President and Chief Financial Officer Kevin Palatnik to Present at the Cowen & Co. Technology, Media and Telecom Conference30 Apr 2009 Cadence Kicks Off Worldwide User Conferences with CDNLive! EMEA 200929 Apr 2009 LFoundry Introduces Industry-Leading Process Design Kit for Cadence Virtuoso IC 6.1 Custom Design Platform29 Apr 2009 Cadence Reports Q1 2009 Financial Results28 Apr 2009 Cadence Senior Vice President and Chief Strategy Officer Charlie Huang, Ph.D. To Present At 1st Asia Symposium on Quality Electronic Design Conference21 Apr 2009 Cadence Senior Vice President And Chief Financial Officer Kevin Palatnik To Present At The JPMorgan Technology, Media And Telecom Conference21 Apr 2009 Cadence and TSMC Introduce Mixed-Signal/RF Reference Design Kit in 65nm Process Technology10 Apr 2009 Cadence Announces First Quarter 2009 Financial Results Webcast09 Apr 2009 Cadence Expands Channel Partner Network in China02 Apr 2009 Global Unichip Announces Greater Than 3X Schedule Reduction of Full-Chip Design Closure on 50M Gate Design with New Encounter Digital Implementation System
 
March

31 Mar 2009 Cadence Captures EDN Innovation Award31 Mar 2009 Cadence Launches 'Industry Insights' Design Community Blog30 Mar 2009 Cadence and NEC Electronics Announce Encounter Digital Implementation System To Support NEC Electronics' System LSI with Built-In V850 CPU Core27 Mar 2009 Cadence President and Chief Executive Officer Lip-Bu Tan to Host Annual Meeting of Stockholders25 Mar 2009 Sequans Speeds Tapeout of 65-Nanometer Mobile WiMAX Single Die Baseband Chip with Cadence Low-Power Solution23 Mar 2009 Cadence End-to-End Solutions Power HuayaMicro to Achieve First Silicon Success16 Mar 2009 Cadence Enhances Low-Power Solution Enabling More Predictable Power-Efficient Design11 Mar 2009 SiS Joins Power Forward Initiative To Assist In Delivering Power-Efficient Computing Platforms03 Mar 2009 Cadence End-to-End Design Solutions Enable UPEK to Consolidate Seamless Full-Chip Design Flow
 
February

25 Feb 2009 OVM Extended to Efficiently Manage Coverage Metrics25 Feb 2009 AMD Selects Cadence Incisive Palladium Series To Verify Complex Graphics Design24 Feb 2009 Cadence Senior Vice President and Chief Financial Officer Kevin Palatnik to Present at the Morgan Stanley Technology Conference23 Feb 2009 Cadence Incisive Verification IP Portfolio Delivers 'All-in-One' Flexibility and Higher Value for SoC Developers23 Feb 2009 Cadence Extends the Open Verification Methodology Beyond SystemVerilog to Include SystemC and e Language Support11 Feb 2009 Adaptive Chips Adopts Cadence Incisive Verification Solution with the Open Verification Methodology (OVM)09 Feb 2009 Cadence Incisive Palladium III Shortens Sharp's System Design and Verification Cycle09 Feb 2009 Customer Testimonials for Semiconductor IP Added to ChipEstimate.com04 Feb 2009 IP Vendors to List TSMC Compatible Cores on ChipEstimate.com04 Feb 2009 Cadence Reports Q4 2008 Financial Results04 Feb 2009 Cadence ChipEstimate.com IP Ecosystem Wins 2009 DesignVision Award
 
January

21 Jan 2009 New Cadence Encounter Digital Implementation System Used by STMicroelectronics for 40- and 32-Nanometer Flows20 Jan 2009 Freescale Japan Adopts Cadence Low-Power Solution To Develop Advanced Power Management Chip20 Jan 2009 Cadence Expands C-to-Silicon Compiler with High-level Synthesis Support for Altera and Xilinx FPGAs15 Jan 2009 STARC Qualifies Cadence Encounter Conformal Constraint Designer for STARCAD-CEL Flow12 Jan 2009 Cadence Low-Power Solution Enables Fujitsu Microelectronics Tapeout of 65nm WiMAX Design09 Jan 2009 Media Advisory: Cadence Announces Fourth Quarter 2008 Financial Results Webcast08 Jan 2009 Cadence Appoints Lip-Bu Tan President and Chief Executive Officer