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03 Feb 2016 Cadence Reports Fourth Quarter and Fiscal Year 2015 Financial Results02 Feb 2016 Media Alert: Cadence to Host Embedded Neural Network Summit02 Feb 2016 New Cadence Modus Test Solution Delivers Up to 3X Reduction in SoC Test Time 01 Feb 2016 Cadence Announces Complete Digital and Signoff Reference Flow for Imagination Technologies’ PowerVR Series7 GPUs

26 Jan 2016 Media Alert: Qi Wang to Keynote Asia and South Pacific Design Automation Conference 201626 Jan 2016 Kandou Uses Cadence Analog/Mixed-Signal Timing and Power Signoff Tools to Deliver High-Speed SerDes PHY IP Design on 28nm Process20 Jan 2016 Cadence Sigrity 2016 Portfolio Improves Product Creation Time with PCB Design and Analysis Methodology for Multi-Gigabit Interfaces18 Jan 2016 HiSilicon Adopts Cadence Innovus Implementation System for Production DSP Designs13 Jan 2016 Arrow Electronics and Cadence Collaborate to Accelerate the Development of Production-Ready Products for Hardware Engineers13 Jan 2016 Media Alert: Cadence to Showcase Signal Integrity Solutions for System-Level, Power-Aware Multi-Gigabit Interface Compliance at DesignCon 201611 Jan 2016 Cadence Tempus Timing Signoff Solution Surpasses 200 Tapeout Milestone Within Two Years of Product Inception08 Jan 2016 Cadence Announces Fourth Quarter and Fiscal Year 2015 Financial Results Webcast 06 Jan 2016 Cadence Tensilica HiFi Audio DSP Becomes First IP Core Approved for Dolby MS12 Multistream Decoder05 Jan 2016 DSP Concepts Enhances Audio Weaver to Support Cadence Tensilica HiFi DSPs 04 Jan 2016 dbx-tv Total Technology Now Available on Cadence Tensilica HiFi Audio/Voice Processors