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Semiconductor Industry Gathers at Cadence CDNLive! India 2012 to Share Best Practices
Winners of CDNLive! India 2012 Best Paper Awards and Cadence India Design Contest Announced

BANGALORE, India, 12 Oct 2012

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, successfully concluded its annual conference CDNLive! India 2012 in Bangalore. Over 870 delegates attended the conference, which for the first time was held over two days, October 10 and 11. The winners of the CDNLive! India 2012 Best Paper Awards and Cadence India Design Contest were also announced at the event.

CDNLive! is an event that brings together Cadence® technology users, developers, and industry experts to share best practices on critical design and verification issues, and to discover new techniques for realizing advanced silicon, SoCs, and systems. This year’s program featured 46 in-depth technical presentations over six parallel tracks.

“CDNLive! provides an excellent platform where our customers and partners can network, exchange ideas, and discuss key industry and technology trends, said Jaswinder Ahuja, corporate vice president at Cadence. “The growing interest in electronics was reflected in both the increased number of attendees and number and quality of abstracts submitted.”

The best paper award winners in each of the categories are:


Paper Title



Invalid Instruction Exit Protocol Verification for Processors Using Formal Techniques

Interra Systems & Texas Instruments

Digital Implementation

Challenges In Implementing 2 Ghz+ High Speed A9 Processor In Cadence Hierarchical Flow


System Verification

Verifying big.LITTLE Using The Palladium-XP


Digital Front End

SmartScan+OPMISR: A Novel Scan Compression Architecture For High Multi-Site Testing

Texas Instruments


Timing Models For Analog IPs Considering Crosstalk Effects


PCB Design & IC Packaging

Die To Die Bonding Using Copper Pillars


The Cadence Design Contest
Cadence also announced the winners of the Cadence Design Contest 2012. This is the seventh year that the contest has been held for students at universities and colleges in India and the winners represent a range of design technologies. The winning entries were KSIT in the Bachelor’s category for their submission titled "Design and Implementation of Low Power Pipelined FFT Processors Using Self -Timed Adders”; and IIT Bombay in the Master’s category for their submission “Low Power, Low Noise Signal Conditioning Chip with Differential ‘Resistance to Frequency’ Converter for Resistive Bridge Sensors”.

The Cadence India Design Contest, launched in 2005, is an annual contest established to increase awareness and generate interest in digital, analog and board design among engineering students at the undergraduate (Bachelor’s) and graduate (Master’s) level. The contest gives students a platform to showcase their innovations in electronic design using Cadence’s EDA technologies and is open to students in India who have access to Cadence tools and technologies through colleges and universities that subscribe to the Cadence India University Program.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

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