Fuji Electric Cuts Development Time 25 Percent with Cadence Virtuoso Accelerated Parallel SimulatorA Leading Power Management IC Company, Fuji Electric Deployed the Cadence Technology to Verify Power Management ICs and Entire SystemSAN JOSE, Calif., 05 Oct 2011
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Fuji Electric reduced by 25 percent both the development time for power management ICs and the verification time for systems by deploying the Cadence Virtuoso Accelerated Parallel Simulator
. The Japanese power management IC company used the simulator in the robust Cadence Virtuoso Analog Design Environment, resulting in dramatic time savings while helping improve quality.
“More and more leading companies are recognizing the time-to-market advantages they can attain by using the Cadence Virtuoso Accelerated Parallel Simulator,” said John Pierce, product marketing director, custom simulation, Silicon Realization at Cadence. “Integrating tightly and seamlessly with the Virtuoso Analog Design Environment, the simulator beats baseline SPICE simulation performance and enables companies like Fuji Electric to conduct more thorough, comprehensive verification, reducing risk and improving quality.”
Fuji Electric develops power management ICs and the power devices that use these ICs for new energy, green IDC, and automotive applications. The Virtuoso Accelerated Parallel Simulator was among the technologies required to perform a conceptual design and to verify a full-chip system.
“Our design team shifted from our traditional approach for a conceptual design to the Virtuoso Accelerated Parallel Simulator-based circuit simulation environment for the entire design process, and achieved the 25 percent reduction in the lead-time for custom/analog design,” said Dr. Naoto Fujishima, general manager of Device Development Dept., Si Device Development Center, Electronic Device Laboratory of Fuji Electric. “In addition, the combination of Verilog-A models and the Virtuoso Accelerated Parallel Simulator further speeds verification time and allows design teams to verify a whole system with a shorter lead time. As a result, we are able to deliver high quality devices with the shortest lead time.”
The Virtuoso Accelerated Parallel Simulator, part of Virtuoso Multi-Mode Simulation, performs high-performance SPICE-accurate simulation for faster convergence on design goals while offering scalable performance and capacity.
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