Cadence Digital and Custom/Analog Tools Included in TSMC Reference Flows to Enable 16nm FinFET DesignsSAN JOSE, Calif., 19 Sep 2013
- Digital design tools support TSMC 16nm Reference Flow using a 16nm FinFET quad-core design with an ARM Cortex-A15, pairing the most advanced geometry with the high-performance ARM Cortex mobile processor
- Custom/analog design tools support TSMC 16nm Custom Design Reference Flow with optimized 16nm native SKILL PDKs, granting designers immediate access to the most advanced Virtuoso features
- Cadence tools, including new Tempus Timing Signoff Solution, are under TSMC V0.5 tool certification and continue to move toward meeting V1.0 requirements
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that its digital, custom and signoff tools have implemented methodology innovations that allow customers to achieve TSMC’s 16nm FinFET process benefits of higher performance, lower power consumption and smaller area. The TSMC 16nm Custom Design Reference Flow development is built on top of the ongoing 16nm FinFET tool certification, which is currently at V0.5 of Design Rule Manual (DRM) and SPICE. Both companies will continue the certification all the way to V1.0. The Cadence® digital design tools were applied in a 16nm FinFET quad-core design that incorporated an ARM® Cortex™-A15 mobile processor for the validation of methodologies in TSMC’s 16nm Reference Flow, with the goal to boost customer design power, performance and area (PPA). The flow was implemented with the Cadence Encounter® Digital Implementation System and includes Cadence signoff tools: Physical Verification System, QRC Extraction, Tempus™ Timing Signoff Solution and Encounter Power System.
The TSMC 16nm Custom Design Reference Flow incorporates the use of optimized 16nm native SKILL® process design kits (PDKs) to enable an innovative FinFET custom design flow by applying a number of fins at every design stage, together with a robust set of productivity-enhancing Virtuoso® capabilities for leading custom/analog design. New capabilities include FinFET custom placement using module generators (modgens), FinFET auto-alignment and abutment, advanced rule support for layout automation, and fluid guard ring generation. Custom/analog tools in the flow include Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Analog Design Environment, and Spectre® Simulator. Signoff tools in the flow include QRC Extraction, Physical Verification System and Virtuoso Power System.
“As more electronics companies turn to 16nm FinFET technology for power savings and performance advantages, it’s important they know their design tools and manufacturing process have been tested to ensure they work seamlessly together,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “The inclusion of these Cadence technologies in TSMC Reference Flows helps our customers meet their time-to-market goals and stay competitive in advanced technology design.”
“Our early investment in FinFET technology development and our longstanding partnership with TSMC continue to create paths to the most advanced chip development in the world,” said Dr. Chi-Ping Hsu, chief strategy officer and senior vice president of the digital and signoff group at Cadence. “We now have many customers using these flows to manufacture chips at TSMC that will soon be powering tomorrow’s state-of-the-art mobile devices.”
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Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here