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Fujitsu Adopts Cadence Chip Planning Technology
Technology Giant Deploys Cadence IC Planning Products to Provide New Design Environment for ASIC Users

SAN JOSE, Calif., 20 Jul 2010

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Fujitsu Semiconductor Ltd. has adopted Cadence® chip planning technology for its design teams while incorporating the technology into its own Web site for customers. The technology giant adopted the Cadence Chip Planning System and InCyte Chip Estimator to improve and speed chip development. In addition, the two companies worked together to incorporate Cadence chip planning technology into Fujitsu’s Japanese Web site so that ASIC users can easily explore the feasibility of ASIC design development.

“Our customers used to check design feasibility with us multiple times in the architectural planning stages, where design specifications were not yet fixed, and that was a significant burden for them,” said Kouichi Ohtsuki, general manager, ASIC and COT Division of the Advanced Products Business Unit at Fujitsu. “So we collaborated with Cadence, who has broad experience with chip planning technology, to create the interface to our Web-based, free chip estimation solution called GA-Estimator. By adopting the Cadence Chip Planning System and InCyte Chip Estimator, we have been able to develop a system that has an excellent user interface, and by using GA-Estimator, our customers can evaluate the feasibility real time on various designs.”

GA-Estimator enables Fujitsu customers to access 180-nanometer gate-array technology through Fujitsu’s Web-based chip estimation solution. Customers can enter specifications and alter the variables so they can consider the tradeoffs before settling on a final design plan. Fujitsu will deploy the solution on its Japanese Web site.

Similarly, the Cadence Chip Planning System enables early and accurate IC estimation, allowing tradeoffs among chip size, power consumption, cost, and time to market. The Cadence InCyte Chip Estimator enables rapid architectural what-if analysis to optimize design specifications. Users can reduce chip size, power, and cost without sacrificing performance.

“Our chip planning technology can help customers grow their business and narrow the profitability gap through a cost-effective path to Silicon Realization,” said Adam Traidman, general manager of the Chip Planning Solutions group at Cadence. “Fujitsu recognizes the benefits of smart chip planning, and is now passing these capabilities along to its customers.”

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
408-944-7226
dsolov@cadence.com


Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc., in the USA and other countries. All other marks and names are the property of their respective owners