New Cadence Energy-Efficient PCI Express IP Helps Reduce Power Consumption for Datacenter and Enterprise ApplicationsSAN JOSE, Calif., 26 Jun 2013
- Innovative circuit calibration technique in new Cadence® PCI Express® 3.0 solution enables customers to meet aggressive active power goals.
- Advanced power and clock management capabilities reduce standby current by 100X
- Optimized transition time latency between active and sleep states
Addressing the design challenge of reducing energy consumption of power-hungry datacenters and enterprise applications, Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced new design IP for low-power PCI Express (PCIe®) development. The new Cadence PCIe Controller and PHY solution enables customers to meet their design goals for active and standby power and exit latency through innovations in circuit calibration, power and clock management, and PLL technology.
Typically, datacenters are only running at peak usage 20 percent of the time. Achieving optimal energy efficiency during these peak usage times, as well as during idle times, is a datacenter industry challenge. The new PCIe IP from Cadence supports x16 configuration, giving designers the maximum performance along with virtualization support to service multi-threaded applications. With the additional support of the latest low-power PCIe L1 PM Substates Engineering Change Notice (ECN) across all Cadence PCIe IP, Cadence is able to provide both low power and high performance during peak operation and system power savings during idle operation.
“The PCI Express L1 PM Substates ECN provides significantly improved power savings over the current L1 Substates, and helps bring improved energy efficiency to a vast array of platforms,” said Al Yanes, PCI-SIG president and chairman. “Member companies like Cadence provide important IP solutions to allow SoC developers to fully exploit the power efficiency mechanisms provided by our flagship PCIe architecture.”
“With datacenters responsible for two to three percent of worldwide energy consumption, advanced technology like our new PCIe IP can have a significant impact for our customers and end consumers,” said Martin Lund, senior vice president, SoC Realization Group at Cadence. “Leveraging Cadence’s many years of high-speed SerDes design, our new PCIe 3.0 controllers and PHY will help our customers reduce leakage power consumed by the PCIe interface from milliWatts to microWatts.”
Cadence offers a comprehensive portfolio of PCIe products that includes controllers and PHYs that span the spectrum from 2.5GT/s (single-lane Gen1) to 128GT/s (16-lane Gen3) with support for advanced features such as virtualization and bifurcation. Cadence provides the rare combination of customization and performance to its controllers, giving designers greater flexibility within their system-on-chip (SoC) design. Like the controller, the Cadence PCIe 3.0 PHY provides flexible lane support and the ability to support wire bond for mobile, client and cost-sensitive applications, and flip chip for enterprise and high performance systems. Cadence has also announced its M-PCIe ™ controller targeted for low-power mobile applications.
For more information about this new IP and other design IP from Cadence, visit www.cadence.com/site/ip/interface
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Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com