Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Company Location *

Comments: *

 

TSMC Certifies Cadence Tempus Timing Signoff Solution for 20nm Designs
Key Technologies Required for Fast, Efficient Signoff of Advanced Node Designs

SAN JOSE, Calif., 22 May 2013

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that TSMC has certified the new Cadence® Tempus™ Timing Signoff Solution at 20 nanometers. The certification means the Cadence Tempus Timing Signoff Solution passes TSMC’s rigorous EDA tool certification to enable customers to achieve accuracy required for advanced technologies.

“Tempus timing signoff technology elevates timing analysis performance to a new standard by leveraging distributed processing and innovative incremental timing technology,” said Anirudh Devgan, corporate vice president, Silicon Signoff and Verification, Silicon Realization Group at Cadence. “We worked closely with TSMC to ensure that Tempus results met their strict criteria that leads to working silicon and robust designs.”

TSMC accuracy certification requirements for the Tempus Timing Signoff Solution spanned base delay calculation and signal integrity with glitch bump calculation. These two areas are required in order to have a complete timing and signal integrity analysis solution.

“Certification is an integral part of TSMC’s overall design ecosystem,” said Suk Lee, TSMC senior director, design infrastructure marketing division. “Cadence Tempus timing signoff tools are ready to address the design challenges of future TSMC process nodes. We worked closely with Cadence so Tempus could pass our acceptance criteria, and we look forward to teaming with them on future technologies.”

The Cadence Tempus signoff technology offers:
  • High-performance parallel processing for full flow timing analysis
  • Scalable architecture to handle designs with hundreds of millions of cells
  • Tempus integrated closure environment, which provides for MMMC (multi-mode, multi-corner), physically aware timing closure with multi-threaded and distributed timing analysis

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
408-944-7226
dsolov@cadence.com


Cadence and the Cadence logo are registered trademarks and Tempus is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.