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Key RF Technologies from Cadence Qualified for TSMC 65-Nanometer Node
Cadence QRC Extraction and Virtuoso Passive Component Designer Now Included in TSMC Process Design Kit to Address RF-Critical Challenges

SAN JOSE, Calif., 14 Apr 2008

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced the qualification of Cadence® QRC Extraction and Virtuoso® Passive Component Designer for the TSMC 65-nanometer process design kit (PDK).

The newly qualified technologies deliver tested and proven inductance, substrate extraction and passive component design. Cadence QRC Extraction handles parasitic inductance and substrate extraction, while the newly released Virtuoso Passive Component Designer technology tackles inductor synthesis, analysis and modeling. In June, Cadence and TSMC introduced a TSMC CompatibleSM 65-nanometer RF PDK using the new Cadence Virtuoso custom design platform, and accompanying downloadable RF, analog and mixed-signal (RF and AMS) design-flow demonstration packages for wireless designers.

The Cadence technologies were qualified as part of the new TSMC Electromagnetic (EM) Tool Qualification Program, which targets TSMC 90- and 65-nanometer process technologies. The program ensures greater electromagnetic accuracy for high-speed digital clock circuits and high-frequency mixed-signal RF design flows.

"Validation of Cadence technologies on our 65-nanometer process node enables designers to build single-chip wireless applications by integrating RF transceivers and synthesizers on to the same SoC with digital baseband and application processors," said Tom Quan, deputy director of Design Service Marketing at TSMC.

Baseband circuits, microprocessors and memories move to the most advanced CMOS process node available. To enable wireless system on chip, RF transceivers and frequency synthesizers must be implemented on the same process. Using Cadence QRC Extraction sign-off accurate modeling of the substrate and RLCK extraction of interconnects, RF designers can increase first-pass silicon success and reduce the cost of over design. What-if analysis with noise contour maps enables designers to rapidly experiment with different placement alternatives of RF blocks in the vicinity of noisy digital circuits.

The TSMC 65-nanometer PDK includes scalable inductor and transformer models validated with Virtuoso Passive Component Designer. Model accuracy has been verified to be within a few percent of measurements for inductance, quality factor and self-resonance frequency. Designers are no longer confined to a limited set of PDK inductors. Starting from design specifications such as inductance and quality factor, RF designers can create their own inductors and transformers in Passive Component Designer using scalable parameterized cells provided in the TSMC PDK. The new technology reads TSMC 65-nanometer rule files and synthesizes components that are DRC- and LVS-clean and ready for Cadence QRC Extraction analysis. The Virtuoso Passive Component Designer supports 65-nanometer effects such as bias, erosion, metal fills and slotting.

"Cadence offers a complete RFIC design flow that combines system design, RF component design, circuit design, simulation, layout and physical verification," said Sandeep Mehndiratta, product marketing director at Cadence. "Cadence QRC Extraction now delivers the most comprehensive parasitic extraction, which includes accurate self and mutual inductances, as well as silicon-proven substrate effects extraction solutions—both critical for RF post-layout verification. Virtuoso Passive Component Designer enables designers to create custom inductors and transformers to meet their design specifications."

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,300 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com

For more information, please contact:
Dean Solov
Direct:408.944.7226
dsolov@cadence.com
Cadence Design Systems, Inc.


Cadence and Virtuoso are registered trademarks, and the Cadence logo is a trademark, of Cadence in the United States and other countries. All other trademarks are the property of their respective owners.