Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced major enhancements to its Virtuoso®-based custom/analog flow, boosting productivity across the entire flow from initial design specification to final GDSII and for process nodes down to 20 nanometers. The expanded custom/analog flow--spanning design, implementation, and verification--includes methodology improvements to help designers manage design parasitics
, a DFM capability
integrated within the Virtuoso environment, and the integrated Virtuoso Power System
, which provides a signoff-accurate way to manage power and signal integrity issues. These enhancements, and many more, are aimed at boosting designer productivity across all process nodes.
“We needed to make a choice between continuing with point tools or embracing a connected methodology,” said Dave Smith, director of engineering at Wolfson Microelectronics. “We chose the unified custom/analog flow from Cadence because we felt it was the best connected and most streamlined methodology. Teaming with an EDA leader not only gives us state-of-the-art tooling but gives us access to expert knowledge in the field, which are essential elements in support of our continued growth.”
The unified custom/analog flow offers enhancements including in-design DFM capabilities integrated within the Virtuoso environment that automatically locate and fix potential DFM violations concurrently during the design process, enabling design teams to confidently address manufacturing variability. Another significant element of the flow is the introduction of the new Cadence® Virtuoso Power System. The Virtuoso Power System provides an integrated, comprehensive, and signoff-accurate way to manage power and signal integrity issues in-design – including IR drop and electromigration caused issues such as shorts and hotspots. And parasitic-aware design features provide early exploration of implementation effects—such as interconnect and device parasitics, electromigration and IR drop, well proximity effects, and litho-induced variability—thus limiting costly late-stage iterations.
Critical new editing, estimation, and automation features help deliver unified intent, abstraction and convergence throughout the flow, essential for optimal Silicon Realization
. Such new capabilities in the Virtuoso v6.1 environment enable even greater layout productivity, enhanced data-sharing around the globe, and seamless technology integration.
A new waveform viewer—tuned for handling large transient simulation databases—eliminates the need for design teams to buy and integrate a similar third-party tool. Other enhancements include automated constraint checking; a new design-rule editing engine designed to handle the complexity of advanced node rule sets; and an interactive short locator that guides the designer through a find-and-fix process for difficult layout-versus-schematic errors.
Finally, the Virtuoso Accelerated Parallel Simulator’s new distributed SPICE capabilities extend designers’ productivity for realizing design intent from specification within the Virtuoso Analog Design Environment to foundry-qualified SPICE models by harnessing the power of the latest hardware available at our customers.
“A unified custom/analog flow enables our customers to achieve a faster path to silicon success than patching together point tools,” said David Desharnais, group director, product management at Cadence. “With the bold enhancements we’ve made to our Virtuoso flow, users can expect the utmost in productivity and predictability for their complex custom, analog and mixed-signal designs.”
The unified custom/analog flow, available immediately, embodies the tenets of the EDA360
vision and delivers on the unique Cadence end-to-end approach to Silicon Realization through pervasive design intent, abstraction and convergence.
The flow brings a truly holistic approach to analog, custom digital, RF, silicon/package co-design, and mixed-signal design, implementation and verification. Key elements of unique intent, abstraction, and convergence in the flow include: Intent
- Built-in publishing and design checking software facilitates maintaining design intent in a globalized work force
- Support of the Common Power Format ensures design intent is maintained across analog/digital domains
- Analysis of pre-extraction parasitics helps model the potentially detrimental parasitic effects and guards against them
- Simultaneous top down and bottom up full-custom floorplanning enabling advanced high altitude visualization and increasing custom layout productivity
- Use of fully integrated VerilogA, VerilogAMS and Wreal models for mixed-signal simulation enabling higher performance at all levels of validation
- Uses signoff-proven engines within the Virtuoso environment, enabling a more efficient “correct-by-construction” design methodology that eliminates lengthy signoff iterations
- New automation to enable automated and concurrent find-and-fix methodologies for LVS, DRC, and DFM optimization in-design
Virtuoso-based Silicon Realization custom/analog flow delivers significant productivity boosts, with customers consistently reporting gains of 25 to 30 percent over the use of point tools. The flow includes Virtuoso Schematic Editor, Virtuoso Analog Design Environment, Virtuoso Multi-Mode Simulation technologies, Virtuoso Layout Suite, Virtuoso Power System, and Virtuoso DFM.
The enhancements to the Cadence custom/analog flow come on the heels of the Jan. 31 announcement of a unified digital flow