Cadence End-to-End Design Solutions Enable UPEK to Consolidate Seamless Full-Chip Design FlowBiometric Fingerprint Security Pioneer Achieves Predictable Time-to-Market and Boosts Design Productivity for Digital, Analog and Mixed-Signal DesignsSINGAPORE, 03 Mar 2009
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced today that UPEK®, Inc.
, a leader in biometric fingerprint security solutions, has consolidated its design flow and selected Cadence® as the only complete solution supplier for full-chip digital, analog, and mixed-signal designs. The move reaffirms Cadence’s leadership in providing end-to-end design solutions for some of today’s most innovative products.
In addition to continued use of Cadence Custom IC Design Solutions, UPEK has switched its full-chip design to Cadence, consolidating end-to-end solutions including the Cadence custom IC solution, Incisive® Design Team Simulator, Virtuoso® Multi-Mode Simulation, and Virtuoso® Digital Implementation including the Cadence Digital Implementation System capabilities, Encounter® RTL Compiler and SoC Encounter, among others. These complete Cadence solutions for digital implementation, analog and mixed-signal full-chip design were deployed by UPEK to achieve first-silicon success and to predictably drive leading fingerprint security ICs to production.
"By adopting these complete solutions from Cadence, we are able to achieve a seamless design flow," said Keng-Soon Yap, director of the Singapore Design Center at UPEK. "The ease of integration among Cadence tools allows us to reduce time-to-market so as to accelerate challenging chip designs for consumer and industrial products. The consolidation also allows us to focus resources on silicon-based technology and application innovations and boost overall engineering productivity."
"In Asia Pacific and elsewhere companies are looking to improve the entire design methodology to reduce risk and hit their market windows by increasing predictability, stability, and reliability in the design environment,” said Lung Chu, President of Asia Pacific and Corporate Vice President. "We have invested significantly in the integration of technologies spanning chip, package, and board design from architectural levels right down through implementation and signoff, all of which enables our customers to achieve predictable, efficient market introductions.”
Extending the production-proven Encounter technologies that designers trust, Encounter Digital Implementation System refines and improves digital design and implementation. It provides a focused, high-performance, advanced design closure and signoff solution for both flat and hierarchical digital designs while also addressing the latest requirements for low-power, mixed-signal, and advanced-node implementation. Similarly, the Cadence Virtuoso custom design technology automates many of the routine tasks in custom IC design, allowing engineers to focus on differentiating their designs.
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Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com
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