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Newsroom
ARM and Cadence have recently announced the tape out of the industry’s first 20nm design based on the ARM Cortex™-A15 MPCore™ processor. The test chip, targeting TSMC’s 20nm process, was jointly developed by engineers from ARM, Cadence and TSMC using a Cadence RTL-to-signoff flow. The milestone announcement is the result of an 18 month collaboration between ARM and Cadence on optimized design flows for the Cortex-A15 processor.
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»
22 May 2012
Media Alert: Cadence Demonstrates Collaboration, Innovation and Technology Leadership at 49th DAC
21 May 2012
Nufront's Third-Generation Mobile Applications Processor Powered by Cadence DDR3/3L/LPDDR2 Memory Interface IP Solution
15 May 2012
Cadence Introduces New NVM Express IP Solutions for Solid State Storage Applications
15 May 2012
Cadence Expands System and SoC Verification Offerings to Accelerate System Integration and Reduce Time to Market
14 May 2012
Netronome Reaps Significant Power, Performance and Area Benefits with Cadence Encounter Digital Technology
10 May 2012
Cadence Vice President of Marketing Pankaj Mayor to Present at the Cowen Technology, Media and Telecom Conference
08 May 2012
Fujitsu Semiconductor Adopts Cadence Chip Planning System for MCU Chips at Its Design Centers Worldwide
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17 May 2012
IPC-2581 Consortium Validates Bare Board Fab Data
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Printed Circuit Design & FAB
14 May 2012
Netronome reduces SoC power use with timing tricks
-
EE Times
14 May 2012
Top 10 Tips for Success with Formal Analysis – Part 3
-
EE Times
09 May 2012
Cutting Edge Technologies Lead Nominations for American Technology Awards
-
Tech America Foundation
06 May 2012
Forte Design Systems joins Cadence Connections program
-
EE Herald
02 May 2012
Cadence Expands OrCAD Capture Marketplace
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Gabe on EDA
02 May 2012
TripleCheck IP validator from Cadence for IP compliance testing
-
EE Herald
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Nancy Szymanski
Cadence Design Systems, Inc.
408.473.8382
nancy@cadence.com
Dean Solov
Cadence Design Systems, Inc.
408.944.7226
dsolov@cadence.com
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