Home > About Cadence > Newsroom > Multimedia Center

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Company Location *

Comments: *

Multimedia Center 


10/22/14
Open-Silicon
Open-Silicon develops complex chips with millions of gates, thousands of clocks, as well as repeatable blocks. Timing signoff and constraints validation can be quite challenging. Tilak Miryala, a design engineer at the company, talks about the limitations of a traditional ECO flow, the advantages of a traditional physically aware ECO flow, and, finally, the benefits of an MC-ECO flow available in the Cadence® Encounter® Digital Implementation System and Tempus™ Timing Signoff Solution.
10/17/14
MegaChips
Designing a networking chip with a hierarchical design can be very challenging in terms of timing correlation between synthesis and implementation and congestion after scan insert. Raghavendra Prasad, a senior design engineer at MegaChips, talks about how much measurable improvement the company gained by applying physically aware synthesis with Cadence® Encounter® RTL Compiler with Physical. Watch the video to learn how to avoid surprises in layout.
10/08/14
PMC
Using a traditional FPGA-based prototyping solution, PMC experienced system bring-up times that lasted from a week to two months. To speed up the process, while also using their existing Cadence® Palladium® XP environment, PMC migrated to the Cadence Rapid Prototyping Platform. Now, they can bring up a system in as little as a week and a half. Yogendra Pal, technical manager for product verification, and Ramchandra Vibhute, a staff engineer, tell you how in this 3-minute video.
09/22/14
ams
Engineers at ams AG were frustrated at how long it was taking to verify their mixed-signal designs. If there wasn't enough time in the schedule, the trade-off was to not verify everything, but risk having chips that didn't work as expected. Knowing that they had reached their limits with the hardware, the ams team turned to software for an answer. In this short video, Thomas Moerth, the company's manager of Design Support, Full-Service Foundry, talks about how Cadence® Virtuoso® AMS Designer helped ams complete 2X the number of simulations as was previously possible and how Cadence Spectre® Extensive Partitioning Simulator helped boost simulation speed by 10X.
09/12/14
Dialog Semiconductor
In this video from CDNLive EMEA 2014, Steven Holloway, Principal Verification Engineer of Dialog Semiconductor, discusses how he needed to successfully verify the register map in his parametric projects, while working around complex access policies, rapidly changing specifications, and the need to complete verification in an overnight regression run. Using Cadence's RegVal formal app flow, Holloway was able to automatically generate properties based on specifications, allowing him to run a validation regression on all 900 registers on the chip in six hours of CPU time and quickly debug any problems, all with less set-up time than it would take to put together a test bench.
09/12/14
Test and Verification Solutions
What do you do when you've got an SoC verification project involving a testbench with a mix of different languages? In this 1.5-minute clip, Mike Bartley, CEO of Test and Verification Solutions, talks about how using open-source UVM-ML has allowed his team to reuse its legacy multi-language verification environment in a new UVM testbench environment. The team was able to wrap its Cadence® Incisive® Enterprise Specman Elite® Testbench in a UVM framework.
09/12/14
STMicroelectronics
Samuele Raffaelli, a digital designer at STMicroelectronics, talks about how he and his team used, as a first step in verification, a formal verification methodology based on Cadence's Incisive® Formal Verifier and Incisive Enterprise Verifier for "exhaustive verification of the RTL." Watch the video to learn how the team reduced its verification time from 12 to 8 weeks.
08/27/14
Methods2Business
In this video from CDNLive EMEA 2014, Marleen Boonen, CEO and Founder of Methods2Business, discusses the company's need to build MAC layers for Wi-Fi 802.11n standards to get to market quickly without compromising on verification. Using the Cadence® C-to-Silicon Compiler's High-Level Synthesis Technology and Unified SystemC Modeling Methodology for high-level synthesis, virtual prototyping, and all verification, Methods2Business built not just working IP, but a MAC layer that is highly customizable in terms of power, performance, area, and functionality.
08/18/14
Test and Verification Solutions
An SoC developer needed to speed up the time for verifying the DDR memory controller in its SoC. Mike Bartley, CEO of Test and Verification Solutions, found a faster way to do this by building a testbench with Denali™ memory models and using automated testbench generation via Cadence's Incisive® Enterprise Specman Elite® Testbench. Watch this 3-minute video to hear Mike explain how these tools helped save 50% of the effort on the 4-month project.
08/18/14
Freescale Semiconductor
In this video, Amitesh Khandelwal, a Freescale Semiconductor design manager working on verification and validation domains, talks about the different challenges his organization faces in its SoC environments, from the lack of synergy and reuse to gaps in coverage in its test cases. With the Palladium XP platform, Freescale has gained critical coverage of the gap as well as a solution to quickly find critical bugs.
08/18/14
Dialog Semiconductor
Dialog Semiconductor faced a potentially daunting challenge: reduce the size and cost of its PCBs via embedded passive devices at the substrate level. The company needed a tool that could help migrate from a two-layer BGA substrate to four layers. Rajesh Aiyandra, package design and simulation team leader at Dialog, explains how Cadence SiP Digital Layout helped deliver a smooth migration, from the change in the number of layers to the change in the via specifications.
08/06/14
IBM
Transistor-Level Reliability Analysis for Advanced Node Description: Sangtae Bae, an analog/mixed-signal circuit designer at IBM, designs high-speed interfaces for IBM's server chips. Bae and his team needed a method to verify circuits will operate in silicon, reliably well over expected life of products. In this 4-minute video, Bae explains how reliability simulation in Cadence® Spectre® Accelerated Parallel Simulator (APS) ran from Cadence Virtuoso® Analog Design Environment (ADE) helped IBM perform reliability analysis efficiently and get to market faster with its server chips.
07/08/14
ARM
Rob Kaye, a technical specialist at ARM, covers the advantages of using ARM® Fast Models with Cadence's Palladium® XP verification computing platform and Virtual System Platform in a hybrid use model. With a hybrid approach, you can achieve as much as 60X faster OS boot up over emulation and execute test cases up to 10X faster. Watch the video to learn about other benefits.
06/12/14
Avago Technologies
In this video from CDNLive Silicon Valley 2014, Jason Gentry, master IC design engineer for ASIC products division at Avago Technologies, describes how he used the Cadence® Encounter® digital implementation system's command line interface to add his own route-planner script and Encounter's multi-partition functionality to split the design into more levels of hierarchy. By doing so, Avago completed top-level route and timing closure in a lot less time—hours instead of days or weeks—because they were working on smaller pieces of the design in parallel.
06/12/14
PMC
In this video from CDNLive Silicon Valley 2014, Jurgen Hissen, principal engineer, MSCAD, at PMC discusses an aggressive RF design with distortion problems in the lab, and how a solution was developed in collaboration with Cadence® FAEs using Cadence Spectre® Accelerated Parallel Simulator's distortion summary feature. This solution provided improved visibility into circuit operation to speed up the distortion-sensitive design cycle by 30%, and more deterministic silicon performance leading to fewer disconnects between simulation and lab.
04/23/14
Lattice
Lattice is a global leader in delivering ultra-low power FPGAs for manufacturers of smartphones, small cell networking equipment, and industrial applications. For its customer base, fast time to market, low power, and low cost are important considerations. In this video, Maryam Shahbazi of Lattice's Systems Development Group talks about how the company relies on Cadence® Sigrity™ tools to model its power delivery network, solve power integrity issues, and improve voltage margins.
04/23/14
NVIDIA
Designed for applications including tablets, smartphones, gaming cards, and supercomputers, Nvidia's high-performance, advanced-node application processors have stringent power and performance requirements and complex clocking schemes. In this video, Santosh Navale, a physical design engineer at Nvidia, talks about how Cadence® Encounter® Digital Implementation System CCOpt technology has improved concurrent datapath and clock optimization, the timing closure process, and overall chip performance. With CCOpt technology, Nvidia has been able to meet its tough design goals.
04/16/14
FTD Automation
FTD Automation is a Cadence® channel partner in India. In this video, Mahendra, a Sr. applications engineer at FTD Automation, talks about the time-to-market and scalability benefits of Cadence OrCAD® PCB design tools. These tools, says, Mahendra, help design engineers address challenges including design complexity and cost, with capabilities including fully integrated schematic entry, signal integrity analysis, and place-and-route methodology.
04/09/14
MediaTek
In this video, Andrew Chang, MediaTek corporate vice president, talks about the challenges in creating today's smart devices—complexity, the push for higher performance, and the need for lower power. Chang discusses how the Cadence® Palladium platform has helped MediaTek achieve faster simulation and debug; the company has achieved a 300X speed-up in simulation time, with 6X faster turnaround time. As a result, MediaTek is succeeding in meeting its time-to-market and design quality goals.
03/27/14
PMC
Engineers at PMC were frustrated with their slow, manual process for verifying analog IP and developing functional models. To automate its processes, the company implemented Cadence® Virtuoso® Schematic Editor and a SystemVerilog testbench. In this video, Vivekanand Malkane, technical manager of the mixed-signal verification team at PMC, talks about how much more efficient the team's verification process is.
02/25/14
STMicroelectronics
STMicroelectronics relies on mixed-signal solutions for its Smart Power Technologies. As Livio Frantantonio explains in this video, STMicro needed to increase productivity and quality of results while shortening its turnaround times. The company found its answer in Cadence's mixed-signal solutions, including Virtuoso® Mixed-Signal Flow. Watch this video to learn how STMicro benefited from using the Cadence Unified Mixed-Signal Methodology.
02/24/14
Altair Semiconductor
For Altair Semiconductor, which develops SoCs for smartphones and tablets, fast time to market is critical. Verifying its SoC architecture can be challenging, but the company addressed this with a verification flow based on Cadence® Incisive® Enterprise Simulator, the IEEE 1647, e language, and vManager for regression runs. Noam Meser, system level verification lead at the company, tells why he is "addicted" to Cadence.
02/19/14
NXP
NXP strives to deliver bug-free products such as RFID, NFC and smart card SoCs. Watch this video to learn how design engineer Rajesh Chitturi worked with his team to save 1.5 weeks from their verification cycle while increasing code coverage to 95% using a flow based on Cadence® Incisive® Enterprise Manager, Incisive Enterprise Verifier, and Incisive Metric Center.
02/18/14
Freescale
Freescale wanted to augment its simulation process for longer running test cases, enable its software teams, and have performance validation (for latency, bandwidth, and throughput) in place. Watch this video to hear Paresh Joshi, a principal staff design engineer at the company, explain how the Cadence® Palladium® XP platform met all of these requirements while helping Freescale speed its simulation process and achieve faster builds.
02/03/14
Analog Devices
Watch this video to learn how Analog Devices ramped up engineering productivity using ModGen tools in Cadence's Virtuoso® Layout Suite solution. CAD engineer Eduard Raines explains how his team replaced time-consuming manual processes with an automated solution to create custom programs for high performance, highly matched design structures.
01/21/14
Freescale
Abhinav Nawal from Freescale stepped above the traditional directed test approach for (Common Power Format) CPF low-power verification. He used Cadence® Incisive® Enterprise Manager, Incisive Enterprise Simulator, SimVision debug, and the Incisive Metric Center to find many critical system-level corner case issues, which, left undetected, would have been catastrophic for his SoC.
01/21/14
Analog Devices
Sri Ranganayakulu from Analog Devices applied the Cadence® Incisive® X-propagation simulation and SimVision debug capabilities to speed up reset verification. In this video, he talks about how he caught eight bugs in two designs in less time than it took with the traditional gate-level approach.
01/21/14
STMicroelectronics
Mohit Jain from STMicroelectronics applied Cadence® Incisive® Enterprise Simulator and SimVision debug capabilities for IEEE 1801 / UPF low-power verification to a low-power demonstrator in preparation for use with a production set-top box chip. Watch this video to learn how he reused his existing code successfully, including the power format files and the macro models coded in his Liberty files.
01/17/14
SCKiPIO
SCKiPIO, which develops next-generation broadband access solutions, needed a design methodology and EDA tools to support its development process. Ron Sterenson, VP of R&D, explains how a Cadence® design flow spanning RTL simulation to system verification helped the start-up achieve faster bring-up, verification, and turnaround time. Hear how the Cadence Incisive®, Encounter®, and Palladium® XP platforms supported the small design team's efforts to grow the company.
01/17/14
SilabTech
SilabTech uses digitally assisted analog techniques to create its chips. To streamline the circuit verification process, the company uses Cadence® AMS Methodology Kit, which verifies the RTL in the analog circuit. And to avoid a manual process for circuit calibration, the company uses Cadence Virtuoso® Analog Design Environment XL, which enables the engineers to evaluate tests sequentially. Ravi Mehta, co-founder and technologist at SilabTech, talks about the benefits of both solutions.
12/17/13
ARM
Brent McKanna, ARM® principal design engineer and implementation tech lead for the ARM Cortex®-A57 processor, discusses how the collaboration between his company and Cadence will benefit designers of enterprise and high-end mobile applications. Using Cadence® tools, including the Encounter® platform, ARM got the right topologies on critical paths of the processor, while hitting frequency goals and staying below power and area goals. Watch the video to learn more about reference methodology scripts created by ARM and Cadence to give design engineers a jump start on development with the Cortex-A5 processor.
12/17/13
EDAis
EDAis, a Cadence® Channel Partner, is the biggest EDA tools distributor in Israel serving over 600 customers in industries including military, medical, and automotive. In this 2-minute video, Yael Arbel, who is responsible for selling Cadence OrCAD® PCB design tools, talks about meeting the needs of a very challenging, fast-moving market and why the OrCAD PCB design tools are the most popular in Israel.
12/16/13
EMA Design Automation
Engineers are doing the work of many, and managing libraries that are in chaos. How to make life easier? Manny Marcano, president and owner of EMA Design Automation, talks about how Cadence® OrCAD® and Allegro® PCB design tools deliver the ease-of-use that lets design teams be operational in less than a day, along with the scalability to grow with the teams' needs. As a Cadence North America channel partner, EMA works with the tools to create methodologies and ecosystems for its customers.
12/16/13
Microsemi
Using Cadence® Allegro® and OrCAD® PCB design tools, Microsemi has built a unified workflow with a database of libraries to support smooth collaboration between its different design teams. In this video, Keren Luria, who manages Microsemi's design services team in Israel, talks about how the Allegro and OrCAD PCB design tools have helped her team tap into technical consistency from idea to final product.
12/12/13
Analog Devices
Anthony Agrillo, a layout engineer at Analog Devices, works with a team that needs to build small-scale, non-timing digital blocks to go with the analog blocks in their design. Frustrated at how long their manual process took, the team turned to the Cadence® Virtuoso® Custom Placer and Virtuoso Space-based Router in Cadence's Virtuoso Layout Suite. Watch the video to find out how much time the team is saving and how much more efficient their process is.
12/12/13
Inomize
In developing customized ASICs for its customers, Inomize needed a processor that supports fast time to market while meeting cost, power, and performance requirements. Udi Shaked, Inomize's CEO, explains how Cadence® Tensilica® Xtensa® configurable processors fit the bill.
12/04/13
Bluespec
Chip complexity continues to grow and chip designers are under a lot of pressure to put a lot of software content in their chips. Bluespec helps alleviate some of these pressures with its technologies that support the early use of emulation and FPGA prototyping. George Harper, the company's VP of marketing, explains why a close collaboration with Cadence and the use of Cadence's Rapid Prototyping Platform helped make its hybrid prototyping solutions a success.
12/04/13
Allegro Microsystems
Allegro Microsystems has small, custom digital blocks to implement. By hand, such designs were taking up to three days to complete. With the Virtuoso® Custom Placer and Virtuoso Space-based Router in Cadence's Virtuoso Layout Suite, Allegro cut that place-and-route time down to a less than a day and reduced its block size by 30%. Watch the video to hear what Steve Nedeau, senior IC layout engineer, says about how the tools have made his life easier.
12/04/13
Global Unichip
Watch this video for insights into Global Unichip's successful tapeout of a 20nm testchip with Cadence and TSMC. Albert Li, marketing director at Global Unichip, talks about the collaborative effort and overcoming advanced node challenges such as double patterning and new design rules.
11/25/13
Hyundai MOBIS
Automotive parts manufacturer Hyundai MOBIS was facing electromagnetic interference (EMI) problems with its PCB designs. In this short video clip, Imran Shaik, a project lead on EMI simulations, discusses how Cadence® Sigrity™ PowerSI™ and Cadence Sigrity SPEED2000™ helped the company reduce its PCB testing time and get its products to market faster.
11/25/13
STMicroelectronics
At STMicroelectronics, engineers were presented with a design in the C model, yet the register-transfer level (RTL) would not become available for another five to six weeks. The engineers wanted to make use of this time and start their verification process. In this short video, Karl Herterich, senior IC verification engineer at the company, explains how Cadence and its Incisive® Specman Elite® Testbench helped the team adjust its verification environment so it could work on the C model first, then RTL for signoff. STMicroelectronics gained a shorter verification cycle in the process.
11/12/13
Learn 3 key benefits of Voltus solution
Watch this video to learn how the new Voltus IC Power Integrity Solution from Cadence delivers 10X faster performance than competitive solutions, with SPICE-like accuracy and capacity for up to one billion instances.
11/06/13
STMicroelectronics
At advanced process nodes, new challenges such as layout-dependent effects emerge. STMicroelectronics needed to address these challenges and automate its full custom analog layout flow. Watch this video to hear Preeti Kapoor, a design engineer at the company, talk about using design constraints (specifically, modgens) to create a faster and more accurate DRC clean design.
11/04/13
Touchstone Semiconductor
Taping out 17 different projects over 3 1/2 years seemed like a tall order for Touchstone Semiconductor. But with a helping hand from Cadence Hosted Design Solutions, the startup got its CAD environment set up smoothly and has successfully rolled out 71 high-performance analog ICs since its founding in 2010. Simply put, Hosted Design Solutions lets Touchstone focus on what it does best - designing circuits. Watch this video to hear the company’s VP of engineering, Dr. Jeroen Fonderie, discuss how Cadence helped his company get off the ground.
10/01/13
Avago Technologies
Jack Benzel, Expert Engineer at Avago Technologies, describes how the new GigaOpt technology in Encounter Digital Implementation (EDI) System boosts IC design quality.
09/26/13
Micron Technology
Hear from David Paquet, Sr. CAD Manager and Julie Sulisthio, Sr. CAD Engineer from Micron Technology as they talk about the use of Physical Verification System Constraint Validator in conjunction with Virtuoso Constraint System to validate design intent and improve design quality.
09/16/13
Applied Micro
Sumbal Rafiq, Director of Engineering at Applied Micro, describes the use of the Cadence Encounter RTL-to-GDSII flow to implement the company’s high performance 2.4GHz X-Gene Server-on-chip embedding the world’s first 64-bit ARM processor.
09/09/13
Zenverge
Kent Goodin, Executive Vice President of Engineering, highlights how Palladium XP II helped Zenverge gain an 80x increase of trace depth and 8X faster upload times, allowing the company to exceed time to market goals and engage with customers 6 months early.
09/09/13
Gary Smith EDA
Gary Smith, Chief Analyst at Gary Smith EDA, details the current state of the System Level Verification industry and confirms Cadence’s long standing leading position and how its system-level verification offerings are well positioned to address the ever growing system verification challenges.
08/07/13
STMicroelectronics
Vincent Varo, Design Kit & Support Manager, at STMicroelectronics discusses the use of Virtuoso Integrated Physical Verification System to address the challenges of 20nm designs.
07/25/13
TSMC
Maria Marced, President of TSMC Europe, discusses with Christian Malter, Director Technology Solutions, EMEA, Cadence, the significance of 16nm FinFET technology and highlights their collaboration with Cadence.
07/25/13
TSMC
Maria Marced, President of TSMC Europe, and Christian Malter, Director Technology Solutions, EMEA, Cadence, discuss how customers benefit from the collaboration between the two companies in the mixed-signal space.
07/23/13
STMicroelectronics
Peter Hirt, IP Procurement & IP Partnership Manager at STMicroelectronics, discusses the role of IP in advanced node designs, IP provider requirements and Cadence's comprehensive IP portfolio.
07/23/13
ARM
Keith Clarke, VP for Embedded Processors at ARM, talks about the importance of facilitating mixed-signal designs by partnering with companies such as Cadence, who can provide knowledge and expertise to the ecosystem.
07/19/13
System Development Suite Solution
Frank Schirrmeister, Group Director, Product Marketing – System Development at Cadence details how customers and partners are using or integrate with the System Development Suite for early software development, power, and performance analysis, design verification, and integrating hardware and software designs.
07/10/13
Cadence
Todd Snyder from Bluespec and Matthias Kupka from Cadence discuss the benefits of connecting FPGA-based Prototypes with Virtual Prototypes through the industry – standard SCE-MI interface resulting in accelerated embedded software development and system validation.
06/20/13
City Semiconductor
Chris Menkus, Founder and CEO, City Semiconductor, outlines the benefits of using the solid support and collaboration technology found in Cadence Hosted Design Solutions’ environment to create their new high speed 12 bit Analog to Digital Converter.
06/05/13
Freescale Semiconductor
Hear from Angela Liang, Sr. Mixed-Signal Verification Engineer, at Freescale Semiconductor as she describes how they utilized the Cadence Low Power and Mixed-Signal Solution to verify the company’s Kinetis Microcontroller products targeted for automotive and internet-of-things applications.
06/03/13
ARM and Cadence Collaboration
Hear from William Orme, Strategic Marketing Manager at ARM, and Steve Brown, Director of Product Marketing at Cadence, as they describe the collaboration and use of the Cadence Interconnect Workbench with ARM’s CoreLink System IP to help SoC designers achieve their power, performance and area goals.
06/03/13
Freescale Semiconductor
Hear from Michael Schinzler, Logic Designer at Freescale Semiconductor, as he highlights the use of the Cadence Rapid Prototyping Platform to help verify their e6500 Power Architecture Core.
06/03/13
S3
Hear from Flavio Cali with S3 Group, as he highlights the user experience of Cadence Physical Verification System (PVS) for SoC design.
05/29/13
AMD
Bryan Sniderman, Verification Architect for AMD, introduces the UVM Multilanguage (ML) Open Architecture to simplify verification IP (VIP) reuse.
05/20/13
Cadence Delivers Unprecedented Performance and Capacity in Timing Signoff and Closure
Anirudh Devgan, corporate vice president, Silicon Signoff and Verification, Silicon Realization Group at Cadence, talks about the massive challenges in timing signoff and how the Tempus™ Timing Signoff Solution addresses these challenges with technology innovations that eliminate the signoff bottleneck.
05/15/13
Broadcom
Vahid Ordoubadian, Director - Mobile Platform Group at Broadcom, describes the use of Cadence Palladium XP to validate a new architecture for a complex mobile SoC for mobile platform devices.
02/05/13
ARM, Samsung and Cadence
Dipesh Patel, EVP and GM, Physical IP Division at ARM, Ana Hunter, VP of Foundry at Samsung Semiconductor and Chi-Ping Hsu, SVP, R&D at Cadence discuss the collaboration between the three companies to develop the first 14nm, FinFET implementation of the ARM Cortex A7.
01/24/13
Analog Devices
Rohit Pandharipande, Design Engineer at Analog Devices, details working with Cadence migrating from VMM to the UVM Compliant, Cadence Verification IP (VIP) to verify a Dynamic Memory Controller.
01/22/13
STMicroelectronics
Abhishek Jain, Technical Manager at STMicroelectronics, talks about working with the Cadence Incisive Verification Solution to deploy a UVM multi-language, low-power verification methodology resulting in earlier and integrated verification.
01/22/13
Open-Silicon, Inc.
Hear from Shrikrishna Mehetre and Souvik Mazmunder, with Open-Silicon, Inc., as they highlight the use of Cadence Encounter digital RTL-to-signoff products to achieve 2.2 GHz performance on a 28nm ARM Dual-Core Cortex-A9 processor.
01/22/13
Open-Silicon, Inc.
Kavitha Nagarajan, Lead Engineer — IC Package Design at Open-Silicon, Inc., describes how the company leveraged the Cadence Integrated SPB environment to successfully complete a complex project with a tight deadline.
12/10/12
imec
Antoine Dejonghe, Green Radio Program Manager at imec, highlights the use of the Cadence CPF-Driven Advanced Low-Power Solution that accelerates the company's next generation 4G wireless designs.
11/21/12
Executive Insight: Market Trends Driving the Need for Collaboration
Executives from Cadence, ARM, TSMC, and Broadcom discuss how three distinct trends in the electronics industry result in design challenges that can only be met through close collaboration among EDA companies, software partners, foundries, and IP partners.
09/20/12
Saphyrion
Angelo Consoli, Managing Director at Saphyrion, details how they leverage the Cadence Virtuoso custom/analog flow and design services to develop ASICs High-End ground and space applications.
09/12/12
Duolog
David Murray, CTO at Duolog, discusses collaborating with Cadence to help customers address SoC integration and verification.
08/27/12
Methods2Business
Listen to Marleen Boonen and Vladislav Palfi, from Methods2Business, as they describe how they use the Cadence Virtual Platform and Verum's Analytical Software Design solution tool to debug earlier in the design cycle and ultimately design software faster and more efficiently.
08/02/12
Cadence is Ready for 3D-IC Design
Hear from Samta Bansal, product marketing manager, Cadence, talking about the challenges facing EDA vendors with the commercialization of 3D-ICs, and how Cadence is leading the charge.
08/02/12
Imperas and Cadence Collaboration
Hear from Larry Lapides, Vice President of Sales at Imperas, and Larry Melling Product Manager - Virtual System Platform at Cadence, as they describe the collaboration and use of the Cadence Virtual System Platform along with Imperas' processor models and verification analysis and profiling tools to address challenges of embedded software development for complex SOCs.
08/02/12
S3
Dermot Barry, VP — Silicon Business Unit at S3, highlights how they leverage Cadence mixed-signal solutions to help their customers achieve business success through fast time to market and first time right silicon with the optimized power, performance and area.
07/30/12
imec
Luc Van de hove, President and CEO at imec, details imec's business focus and highlights the collaboration between imec and Cadence.
07/30/12
X-Fab
Dr. Jens Kosch, CTO at X-Fab, highlights the use of the Cadence Mixed-Signal solution to help mutual customers with their designs.
07/17/12
IBM
Nancy Pratt, BIST Verification Lead at IBM, details the use of Cadence Verification tools to help streamline and provide more detailed reports, improve planning and increase scheduled adherence.
07/06/12
NVIDIA
Narendra Konda, Director, HW Engineering at NVIDIA, discusses leveraging Palladium XP and the Rapid Prototyping Platform to integrate complex hardware and software designs.
07/06/12
Freescale Semiconductor
Wai-Chee Wong, Senior Member of Technical Staff at Freescale Semiconductor, details how Palladium XP helps speed their verification effort by 10,000x over simulation
07/06/12
Xilinx
David Beal, Zynq 7000 EPP Product Manager at Xilinx, describes how the Cadence Virtual System Platform helps to accelerate product development.
07/06/12
LeCroy
John Wiedemeier, Product Marketing Manager — Protocol Solutions Group at LeCroy, describes the collaboration with Cadence utilizing PCI Express 3.0 to help mutual customers reduce development risk, improved system interoperability and reduce time to market.
06/22/12
TSMC
Ashok Mehta, Sr. Manager System Verification/Software Architecture describes how they worked with Cadence to Address System-Level Complexity with the TSMC ESL Reference Flow 12.
06/22/12
GLOBALFOUNDRIES
Luigi Capodieci, Director of Design for Manufacturing, R&D Fellow at GLOBALFOUNDRIES, discusses how they collaborated with Cadence on pattern-matching technologies to accelerate full-chip DFM signoff.
06/21/12
AMD
Alex Starr, Hardware Emulation Architect at AMD, highlights the unique capabilities of Palladium XP and in-circuit acceleration.
06/14/12
Silicon Blue Technologies
Andy Chan, Vice President of Engineering at Silicon Blue Technologies details how they utilize the TSMC-certified Cadence DFM Services along with Cadence technologies to develop consumer mobile applications
06/04/12
IBM
Lars Liebman, Distinguished Engineer at IBM, highlights the collaboration between IBM and Cadence in solving design challenges at 20nm and 14nm technology nodes.
03/20/12
Freescale Semiconductor
Anis Jarrar, Principal Design Engineer, at Freescale Semiconductor describes how they utilized the Cadence Low-Power Solution to design and implement the complex Kinetis SoC.
03/20/12
Lip-Bu Tan Honored as Outstanding CEO with 2012 Singapore Business Award
Cadence President and CEO Lip-Bu Tan received the Singapore Business Award as Outstanding CEO (overseas) at a black tie event in Singapore on March 20, 2012.
02/09/12
Xilinx
Larry Getman, Vice President Processing Platform Marketing at Xilinx describes working with Cadence and the Virtual System Platform to developed the Zynq-7000, the industry's first virtual platform for system design and software development.
02/09/12
Xilinx and Cadence
Larry Getman, Vice President Processing Platform Marketing at Xilinx and Michael McNamara, VP and GM System Level Design at Cadence highlight the collaboration between Xilinx and Cadence to develop the Zynq-7000.
01/18/12
BIOTRONIK
David Genzer, Director of IC Development at BIOTRONIK describes how they leveraged the Cadence digital implementation and signoff flow and CPF-enabled low-power solution to help deliver the most advanced and sophisticated pacemaker product on the market.
12/15/11
ARM Tech Con 2011 Fireside Chat between ARM and Cadence
Listen to this informal conversation between Simon Segars of ARM and Lip-Bu Tan of Cadence to hear how they think collaboration is evolving and what's necessary for success in the era of "apps-driven" multicore designs and 20nm implementation. Get an executive perspective on how to evaluate innovation opportunities and how to drive effective collaboration to capitalize on those opportunities.
09/22/11
Global Unichip Corporation (GUC)
Alex Kou, Senior Design Manager at Global Unichip Corporation, highlights how the CPF enabled Cadence Low Power Solution helps them achieve 100+ low power design tape-outs and address their low power design challenges in future technology nodes.
06/06/11
Getting a Jumpstart on 20nm - Part I
Distinguished panelists discuss the challenges and approaches that need to be considered when designing and implementing at the 20nm node. Moderated by Jim Handy, the panel includes Philippe Magarshack - STMicroelectronics, Ana Hunter - Samsung, Simon Segars - ARM, and Chi-Ping Hsu - Cadence.
06/06/11
Getting a Jumpstart on 20nm - Part II
Distinguished panelists discuss the challenges and approaches that need to be considered when designing and implementing at the 20nm node. Moderated by Jim Handy, the panel includes Philippe Magarshack - STMicroelectronics, Ana Hunter - Samsung, Simon Segars - ARM, and Chi-Ping Hsu - Cadence.
05/11/11
Josh Moore
Cadence
Josh Moore, Senior Product Manager for OrCAD, shares how the new OrCAD Capture Marketplace — with online apps — transforms the way PCB designers access information, discover new resources and extend the OrCAD environment.
05/03/11
System Development Suite — Narendra Konda, Director Hardware Engineering, NVIDIA
Narendra Konda of NVIDIA outlines how the Cadence System Development Suite helps his design team successfully integrate complex hardware and software, quickly develop app-ready systems, and ultimately improve the overall quality of their products.
05/03/11
System Development Suite — Nimish Modi, Senior Vice President, System and Software Realization Group, Cadence Design Systems
Nimish Modi of Cadence discusses system development trends, customer challenges, and how the Cadence System Development Suite enables concurrent hardware/software design and verification at every stage of the development cycle.
05/03/11
System Development Suite — Ran Avinun, Marketing Group Director, Cadence Design Systems
Ran Avinun of Cadence discusses software development and system engineering requirements and Cadence solution including the two new platforms: the Rapid Prototyping Platform and the Virtual System Platform to address alternative limitations.
05/03/11
Virtual System Platform — Sanjay Srivastava, SoC realization, Cadence Design Systems
Sanjay Srivastava of Cadence discusses firmware challenges and requirements as part of IP delivery and how Cadence Virtual System Platform helped his team to solve these challenges in order to deliver a high quality software and hardware IP to a Cadence customer on time.
03/23/2011
Hear about 3D-IC/TSV Design Methodology from Cadence R&D
Find out what it takes to handle 3D-IC/TSV design challenges
02/23/2011
Cadence Opens NASDAQ Stock Market
Lip-Bu Tan, Cadence President and Chief Executive Officer and members of the Executive Management Team rang the opening bell at the NASDAQ stock market on Tuesday morning, February 23, 2011.
02/23/2010
Cadence Opens NASDAQ Stock Market
Lip-Bu Tan, Cadence President and Chief Executive Officer and members of the Executive Management Team rang the opening bell at the NASDAQ stock market on Tuesday morning, February 23 marking our 5th anniversary of being listed on the NASDAQ exchange.
02/04/11
Global Unichip Corporation (GUC)
Albert Li, Director of Design and Development at Global Unichip Corporation, outlines the benefits of partnering with Cadence for giga-gate/GHz, 28nm design.
02/01/2011
Silansys Semiconductor
Niall O hEarcain, the CEO of Silansys Semiconductor describes the benefits of partnering with Cadence for advanced RF level and multimillion-gate designs.
02/01/2010
New Encounter Digital Implementation System enables superior design productivity and quality
Sumbal Rafiq, Director of Engineering at Applied Micro Circuits, describes the success with the Cadence Encounter Digital Implementation System.
12/07/2009
Cadence Virtuoso Gets Major Upgrade
Steve Lewis, product marking director for the Cadence Virtuoso technology, discusses the latest productivity, capacity and ease-of-use enhancements to the company's flagship custom IC and mixed-signal product suite.
11/10/2009
A Conversation with John Bruggeman, Cadence Chief Marketing Officer
In this video interview, John Bruggeman talks about his previous marketing experience, his role and responsibilities as the new Cadence CMO, as well as the direction ahead for both Cadence and the EDA industry.
10/19/2009
Cadence-ARM Collaboration
Steve Glaser, corporate vice president of strategy and planning, discusses the collaboration between Cadence and ARM to create a next-generation SoC design flow that accelerates time to market while lowering the cost of SoC integration and verification. The flow provides mutual customers better methods to optimize SoC integration architectures and IP selection, and provides VIP-based automation to speed both performance and functional verification time.
10/14/2009
Tom Anderson Discusses the Expanded Mmulticore Support for Key Cadence Products
Tom Anderson, product marketing director for enterprise verification, discusses the expanded multicore support for many key Cadence products. Cadence engineers have created parallel algorithms to ensure design teams using multicore machines can reap significant performance benefits.
10/05/2009
The Incisive Enterprise Verifier
Sarah Lynne Lundell discusses the new Incisive Enterprise Verifier, which delivers the dual power of formal analysis and simulation engines. Sarah discusses some of the product's unique features—and how they can benefit verification teams deploying them.
05/18/2009
Cadence and Virtutech Extend Metric-Driven Verification to Virtual System Development
In this video, recorded at CDNLive EMEA 2009, Ran Avinun, Marketing Group Director of System Design and Verification at Cadence, describes the combined offerings of Virtutech Simics and Cadence Incisive software extensions and how it improves quality and project predictability for teams creating and using virtual platforms.
05/18/2009
Hemant Shah Comments on Cadence Announcement of FPGA-PCB Co-Design Solution
Cadence introduced an innovative FPGA-PCB Co-Design solution at CDNLive EMEA 2009. Hemant Shah, Allegro PCB Products Marketing Director at Cadence, explains what this announcement is about through a very short Q&A session.
06/19/2008
San Jose Mayor Chuck Reed Honors Cadence Design Systems
San Jose Mayor Chuck Reed honors Cadence on its 20th anniversary by declaring June 19, 2008 Cadence Day.
06/16/2008
Cadence Corporate Overview
Consumers continue to demand sleeker, faster, thinner, and ever more functional electronic devices. Cadence is proud to lead in providing the innovative software that enables our customers to achieve breakthrough results. Take a look to see more of why we are in the things you can't do without.
06/1/2008
Cadence among the best in Silicon Valley
Last November, Cadence was included in a list of the 50 Best Places to Work in Silicon Valley by San Jose Magazine. As a result of our placement, on June 1, Cadence was featured on the CBS 5 - KPIX television show, Best Places to Work, along with several other leading Bay Area companies.
04/28/2008
CDNLive! 2008 EMEA
A successful CDNLive! EMEA recently concluded in Munich, Germany. More than 620 customers representing more than 200 European and international companies attended the event. The event centered on the Cadence product roadmap, EDA techtorials, and Designer Expo, and proved to be a constructive networking platform for discussing the various challenges of electronic design automation. In this podcast we hear customers and guest speakers talking about their experience attending the event and it will give you an excellent view on the EDA industry get-together.