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New Cadence Kit Enables Engineers to Adopt Functional Verification Methodology Faster and with Less Project Risk

Today's wireless and consumer chip designs are becoming increasingly complex, which puts pressure on design teams to apply more effective verification methods and technologies. Cadence® kits help IC designers to accelerate technology-specific product development and address design challenges in various EDA technology segments. Now Cadence has launched a new kit that enables engineers to more rapidly adopt advanced verification techniques with reduced risk and less deployment effort to meet their shrinking time-to-market requirements.

The Cadence SoC Functional Verification Kit provides a proven end-to-end methodology that extends from architectural modeling, RTL block to chip, and system levels—all running on a realistically complex Cadence SoC wireless design using an ARM processor model. It delivers relevant methodologies utilizing an interactive approach for designers, verification engineers, and management. The kit comes with verification plans, transaction-level models, design and verification IP, scripts and Incisive Plan to Closure (IPCM) tutorials. These can be used immediately and are all delivered to customers though workshop modules, over 40 hands on labs, and on-site professional services applicability consulting by experts in their field. Users can implement the entire kit as an integrated flow, or may select flows individually.

The kit demonstrates the latest automation techniques available within the Cadence® Incisive platform, and focuses on the key verification challenges identified by our customers. This approach enables project teams to save weeks to months in their development cycle, while reducing the risk of critical functional errors in the process. Some of the specific focus areas of the kit—which are typical in today's SoCs—include RTL verification of low power modes, protocol compliance of standard communication interfaces, and hardware/software co-verification, which is a critical success factor in all SoCs. All of this is done using the IPCM approach, leveraging coverage-driven verification, formal analysis, and emulation techniques.

The SoC Functional Verification Kit delivers a solution spanning the full verification process to ease adoption of advanced verification capabilities for design and verification teams.Moshe Gavrielov,executive vice president and general manager, Cadence Verification Division.Cadence Design Systems, Inc.

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