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Closing the gap between logical and physical views of a design

Cadence Logic Design Team Solution brings physical predictability to logic design

The Cadence® Logic Design Team Solution offers an early, comprehensive and concurrent metrics-driven approach to front-end design. It enables logic designers to effectively design, verify, and implement their RTL block- and chip-level designs with significant improvements in schedule and quality compared with traditional design and verification processes. A major new enhancement to the solution is a unique "design with physical" component, which brings physical predictability to logic design by giving designers an unprecedented view of the physical model.

Logic designers have long faced uncertainties in the handoff to physical implemtentation teams. Without an accurate view into the effects of physics and real wire delay present in the physical model, they have found it increasingly difficult to achieve predictability, especially as designs have moved to smaller geometries. The result has been lengthy iterations between logical and physical design teams. Logic designers attempted to circumvent this problem by increasing timing margins, which has resulted in unacceptable increases in die size and power consumption.

Now Cadence helps logic design teams improve quality of silicon (QoS)—achieving timing, power, area and schedule predictability through an accurate physical view of the design. This new design with physical approach builds on the industry-leading capabilities of Cadence Encounter® RTL Compiler XL with global synthesis technology by integrating Cadence First Encounter® XL silicon virtual prototyping into the synthesis environment. As a result, logic design teams now can automatically design and synthesize with real physical floorplan data, virtually eliminating disparities between logical and physical timing views.

The Cadence Logic Design Team Solution replaces traditional statistical wireload models with real physical timing information. The RTL-to-gate transformation and optimization process is driven by a proprietary Physical Layout Estimation (PLE) algorithm in Encounter RTL Compiler, which has been proven in over 100 tapeouts to create a better, pre-converged netlist for implementation. First Encounter silicon virtual prototyping capability is then incorporated into the synthesis cockpit to quickly obtain the most accurate view of physical interconnect timing. This all but eliminates disparities between logical and physical timing views.

"This breakthrough solution provides logic design teams with an automated method to ensure accurate timing closure without lengthy iterations with the physical implementation team—a powerful capability that greatly improves the predictability of the design schedule and dramatically increases the quality of silicon," said Nimish Modi, corporate vice president of Front End Design at Cadence.

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