Enhanced Design-with-Verification Approach Speeds RTL Designs by Eliminating Verification Bottlenecks
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The Cadence® Logic Design Team Solution offers an early, comprehensive and concurrent metrics-driven approach to front-end design. It enables logic designers to effectively design, verify, and implement their RTL block- and chip-level designs with significant improvements in schedule and quality compared with traditional design and verification processes. A key pillar of the solution is a unique "design-with-verification" component. Now Cadence has enhanced this technology with new capabilities to address several major verification bottlenecks.
To enable effective assertion-based verification (ABV) early in the design process, it delivers up to 50 times the speed, along with greater capacity, in SystemVerilog Assertion and Property Specification Language-based formal analysis. By combining Cadence Incisive® simulators and Xtreme® accelerators in a single environment, the enhanced design-with-verification approach also lets designers realize up to a 100,000-fold increase in simulation performance.
The new environment lets users hot-swap back and forth between a leading commercial simulation tool and Incisive Xtreme III accelerator/emulator. Additionally, using a new line of assertion-based verification IP (ABVIP) products, environment creation and set-up can be accomplished in as little as one-tenth the time required previously. According to one early user, Sang Tran, Manager VLSI Technology at Newport Media, Inc., "I brought up the verification environment in just 15 minutes. I can say confidently that Cadence’s AHB verification IP saved me several weeks, at a minimum."
With this enhancement, the Cadence Logic Design Team Solution—which integrates technology from the Cadence Incisive functional verification and Encounter® digital IC design platforms—makes design engineers even more productive. "Logic design teams are asked to create increasingly sophisticated products in shrinking geometries while meeting a growing range of design objectives, such as correct reusable functionality and adequate testability," said Michal Siwinski, product marketing group director at Cadence Design Systems, Inc. "This new verification-based component enables logic designers to move from simple simulations with hand-written tests to a more efficient mix of assertions, formal analysis and sophisticated testbenches tuned to the needs of design teams."