Interview: Low-Power Design and Verification using the Si2 Common Power Format
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The Cadence® Low-Power Solution was introduced earlier this year as the industry's first fully integrated flow for logic design, verification, and implementation of low-power chips. Based on the Common Power Format (CPF), an Si2 standard for specifying power-saving techniques early in the design process and preserving design intent throughout the flow, the solution eliminates laborious manual work and reduces power-related chip failure.
While vendor claims can be disputed, actual user experience demonstrates the strength of the Cadence approach to designing, implementing, and verifying low-power ICs. Stylianos Diamantidis, CDNusers.org verification zone forum moderator, interviews Milind Padhye, Wireless Low Power Design Manager at Freescale Semiconductor and Power Forward Initiative advisor. Milind describes some of the challenges of designing and verifying low-power ICs, as well as how "CPF enables a consistent low power design integration and verification flow. This reduces expensive errors and improves the low power concept to silicon cycle time."