Generating excitement at CDNLive! EMEA in Munich, Cadence announced
its new scalable FPGA-PCB co-design solution for designing FPGAs onto PCB systems. The Cadence® Allegro® and OrCAD® FPGA System Planner delivers automated placement-aware FPGA pin I/O assignment synthesis to reduce risk and shorten the time to design-in complex FPGAs with large pin counts and elaborate banking and pin assignment rules. Already a leader in co-design technologies, Cadence enters a new market space with this innovative FPGA-PCB co-design solution, which provides automated, correct-by-construction pin assignment for FPGAs to speed design cycles and eliminate unnecessary physical prototype iterations inherent to manual pin assignment methods.
The need among systems companies for increased data throughput and more functionality in their products has resulted in large pin-count FPGAs with high-speed I/Os. These FPGAs also have more advanced memory interfaces that consume much less power and address the market trend of developing “greener” products. Use of such FPGAs with greater capacity, more capabilities, and advanced high-speed interfaces has increased in PCBs, as well as for prototyping ASICs using FPGAs on a PCB. The Allegro
FPGA System Planner targets these systems companies and IC companies, helping them differentiate their products and get them on the market quickly.
Traditional approaches to pin assignment are manual and time consuming, performed at the pin-by-pin level in an environment that is unaware of how placement of critical PCB components can impact routing. Changes made to the pin assignment by the FPGA designer must be incorporated in the schematic design by the hardware designer. Design teams are often forced to choose between the lesser of two evils: live with sub-optimal pin assignment (which can increase the number of layers on a PCB and therefore increase cost), or deal with numerous iterations at the tail-end of the design cycle.
The Allegro and OrCAD FPGA System Planner addresses the challenges that engineers encounter when designing one or more large pin-count FPGAs on the PCB board—which includes creating the initial pin assignment, integrating with the sche¬matic, and ensuring that the device is routable on the board. It delivers a complete, scalable solution for FPGA-PCB co-design that automates creation of optimum correct-by-construction pin assignment. This unique placement-aware pin assignment approach eliminates unnecessary physical design iterations that are inherent to manual approaches. With a way to quickly synthesize optimum pin assignment with user-specified design intent at a high level, designers can now explore their FPGA-based architecture and optimize pin assignment for either production or prototype designs that use FPGAs.
"Off-the-shelf multi-FPGA prototyping boards do not always meet the needs of designers," said Ed McGettigan, Senior Director of silicon hardware and applications at Xilinx. "Using this FPGA I/O synthesis technology, designers can create a new prototyping system while rapidly exploring multiple interconnect and component design alternatives much more quickly than by using typical manual methods for pin optimization."
Originally developed by Taray, Inc., and available to Cadence customers through an OEM agreement, this exclusive joint solution works with the Allegro 16.2 release and is ready for immediate adoption. The technology is available in a series of scalable solutions from the OrCAD FPGA System Planner to the Allegro FPGA System Planner L, XL, and GXL tiers, and integrates with OrCAD Capture, OrCAD PCB Designer, Allegro Design Entry HDL, and Allegro PCB Design products.