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Incisive Enterprise Verification Family Gets Big Boost In Performance and Productivity

A new generation of electronics products—such as multi-mode cell phones, game consoles and HD-DVD players—require chips that pack greater performance and more functionality. To address the verification requirements of these increasingly complex chip designs, Cadence has integrated fundamental new technologies into the Cadence® Incisive® Enterprise verification family of products. These exciting performance and productivity improvements span three areas, including major enhancements to Incisive Specman® Testbench, Incisive Enterprise Simulator, and the Incisive Palladium® and Xtreme® hardware acceleration/emulation systems.

Revolutionary New Aspect-Oriented Generation Engine To keep pace with increasing design complexity, Incisive Enterprise Simulator and Incisive Specman now feature a next-generation engine that leverages aspect-oriented programming (AOP). Targeted at advanced verification specialists executing complex, aspect-oriented sequences against large designs, the new engine increases performance by nearly five times for e-based verification environments. To keep pace with increasing design complexity, Incisive Enterprise Simulator and Incisive Specman now feature a next-generation engine that leverages aspect-oriented programming (AOP). Targeted at advanced verification specialists executing complex, aspect-oriented sequences against large designs, the new engine increases performance by nearly five times for e-based verification environments.

"By combining improved performance, built-in planning and management and system-level scalability, we're ready to verify our next generation of designs with confidence," said Thomas Kraus, verification manager at Siemens.

Transaction-Based Acceleration To improve the productivity for system-level verification using Incisive Xtreme and Palladium hardware acceleration/emulation systems, the Incisive Enterprise verification family leverages the next generation of transaction-based acceleration (TBA). This new version, TBA 2.0, is compliant with the Accellera SCE-MI 2.0 draft standard, ensuring automation, ease of use and platform portability while delivering high performance. In addition to providing a number of enhanced capabilities, Xtreme and Palladium systems with TBA 2.0 help design and verification teams reduce their verification time by furnishing new infrastructure and guidelines to support a reusable accelerated verification environment. To improve the productivity for system-level verification using Incisive Xtreme and Palladium hardware acceleration/emulation systems, the Incisive Enterprise verification family leverages the next generation of transaction-based acceleration (TBA). This new version, TBA 2.0, is compliant with the Accellera SCE-MI 2.0 draft standard, ensuring automation, ease of use and platform portability while delivering high performance. In addition to providing a number of enhanced capabilities, Xtreme and Palladium systems with TBA 2.0 help design and verification teams reduce their verification time by furnishing new infrastructure and guidelines to support a reusable accelerated verification environment.

"The new offerings in the Incisive Enterprise verification family enable our users to handle designs containing hundreds of millions of logic gates, addressing the needs of the most advanced verification teams," said Jim Miller, Cadence executive vice president.

Support for Open Verification Methodology Cadence has also added support for the Open Verification Methodology (OVM) and its underlying class library to the mixed-language Incisive Enterprise Simulator. By reducing the time it takes to create SystemVerilog verification environments and ensuring industry-wide code portability and reuse, the new OVM support boosts overall team productivity improves predictability in the verification process. It also helps simplify building and debugging verification testbenches—a process that otherwise becomes increasingly difficult as design complexity escalates. The Incisive Enterprise Simulator also has many additional new features and enhancements affecting all aspects of verification. Cadence has also added support for the Open Verification Methodology (OVM) and its underlying class library to the mixed-language Incisive Enterprise Simulator. By reducing the time it takes to create SystemVerilog verification environments and ensuring industry-wide code portability and reuse, the new OVM support boosts overall team productivity improves predictability in the verification process. It also helps simplify building and debugging verification testbenches—a process that otherwise becomes increasingly difficult as design complexity escalates. The Incisive Enterprise Simulator also has many additional new features and enhancements affecting all aspects of verification.

"The Incisive Enterprise Family delivers the open class-based methodology, advanced debug, and powerful generation we need in our projects, said Michael Hoyt, President and CEO of Paradigm Works.

All together, these three major enhancements to the latest Incisive Enterprise Family, Incisive 6.2, round out a verification solution geared to the most complex chip designs. They boost productivity and improve predictability with up to 5x improved performance, the ability to handle hundreds of millions of logic gates, increased ease-of-use, as well as other capabilities to help you find bugs faster.

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