Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Company Location *

Comments: *

 

Latest Encounter Platform Offers New DFM and Low-Power Features for 65nm Designs

At 65nm and below, designers contend with a wide range of process effects on manufacturability, cell and interconnect delay, leakage and power consumption, signal integrity, and routing. To achieve high yield, it is critical to bring the effects of manufacturability in optimization of timing, area, and power.

The latest release of the Cadence® Encounter® digital IC design platform offers an innovative approach to incorporating advanced low-power design techniques while ensuring manufacturability. New and improved features include yield optimization by Cadence Chip Optimizer, mixed-signal design support, diagonal and lithography-aware routing, and CPF 1.0-enabled low-power design support. With the enhanced Encounter platform, design teams benefit from ease-of-use, fast turnaround time, and high performance while achieving manufacturability and yield for low-power designs at 65nm and below.

The latest release of the Encounter platform represents an important development to the members of STARC because it addresses, in a comprehensive fashion, the challenges inherent in designing for low power and manufacturing, with high productivity," said Nubuyuki Nishiguchi, Vice President and General Manager of STARC. "This integrated, front-to-back approach creates significant value to leading-edge designers.Nubuyuki Nishiguchi,Vice President and General ManagerSTARC

The Encounter platform provides unparalleled DFM and low-power support. Using the new Encounter X Interconnect Option's diagonal routing, designers can optimize tradeoffs among timing, area, and power to achieve high yield quickly and cost-effectively. The platform also features new bus routing capabilities for mixed-signal design and critical path simulation using the Cadence Virtuoso® UltraSim Full-Chip Simulator. With new power-aware automatic macro placement and support for simultaneous multi-mode/multi-corner timing analysis and optimization, designers have a comprehensive solution for the largest, most complex designs at 65nm and below.

Press release

Product Information

Feature stories archive »