Cadence has accelerated digital IC design with the introduction of the new Cadence® Encounter® Digital Implementation System
. It delivers innovative technologies from RTL to GDSII, while providing optimal performance, capacity, and quality of silicon for complex design closure, low power, mixed signal, advanced node, and signoff analysis. End-to-end parallel processing
The Encounter Digital Implementation System extends the production-proven Cadence digital IC design flow with end-to-end parallel processing and other enhanced features. New advanced memory and a completely extensible architecture in a single integrated solution combine to significantly boost both speed and capacity.
In fact, early adopters of the new system are reporting dramatically improved design time and design closure for advanced digital and mixed-signal devices.
According to Wenyuan Lee, Field Design Manager, Kawasaki Microelectronics, "For the complex ASIC designs that we handle at Kawasaki Microelectronics, the requirement to manage different functional modes and process corners for each design is not uncommon. Cadence delivers on a reliable multi-mode, multi-corner timing closure solution that provides consistent results with Encounter Digital Implementation System. A highly reusable methodology, coupled with intuitive design analysis and debugging, results in a more productive environment and a shorter time to tapeout."
Among other areas, the system also improves results at advanced process nodes, where the root cause of parametric variation originates from lithography, etch process, and random defects. “The variability in both clock nets and signal nets exponentially increases timing, power, and yield concerns. Using Encounter Digital Implementation System, we are very pleased to achieve significant Normalized Yield Loss Reduction (NYLR) of 3-6%,” reported Lionel Riviere, Senior Technical Staff Engineer, DFM Development Team, Freescale.
These enhancements not only enable customers to reduce time to market but also to achieve design goals that were not practical using previous technologies.Become an implementation specialist and win cool prizes
We invite you to experience and explore all the dimensions of the new Encounter Digital Implementation System. To celebrate the launch, Cadence has created a process for you to become a specialist in the latest requirements and techniques to address complex flat and hierarchical design closure, advanced signoff, low-power, mixed-signal, and advanced node design. And to keep it exciting, we’ve created opportunities for you to win great prizes you can win along the way. Find out more and get started »
“At advanced process nodes, the root cause of parametric variation originates from lithography, etch process and random defects. The variability in both clock nets and signal nets exponentially increases timing, power and yield concerns. Using Encounter Digital Implementation System, we are very pleased to achieve significant Normalized Yield Loss Reduction (NYLR) of 3-6%.” Lionel Riviere, Senior Technical Staff Engineer, DFM development team, Freescale
“Avago Technologies has successfully designed and manufactured high performance ASICs for over 3 decades. Our designs require leading-edge IP such as our embedded SerDes, and as performance requirements increase, we've seen the number of IP cores in a given block go up as well. Using automatic floorplan synthesis, we have in many cases observed a significant reduction in block floorplan generation time. Avago Technologies is pleased to use Cadence's Encounter Digital Implementation System." – Jack Benzel, ASIC design engineer, Avago Technologies
"The new Encounter Digital Implementation System, coupled with Stratosphere’s ProcessIntelligent characterization and modeling, drives design parametric yield and performance higher by employing statistical timing and leakage power analysis as well as optimization. Together, we continue to enhance the seamless flow from foundry to the designers’ desktop enabling our mutual customers to rapidly adopt and deploy variability-aware solutions - resulting in lower design margins, cost reduction and performance gains in their end-products." - Prashant Maniar, Chief Strategy Officer, Stratosphere Solutions.
"In order to deliver ultra-low power solutions to our customers, our designs are constantly pushing the limits on low power design. Encounter Digital Implementation System's low power technology has a proven track record of enabling us to achieve our power targets by providing a consistent methodology in an integrated environment, as well as consistency with the overall Cadence Low Power Solution." -Andrew Adams, Vice President Engineering, G2 Microsystems
"Low-power design and design for manufacturability are key factors for customers when choosing to adopt the 45-nm Common Platform technology," said Mark Ireland, Vice President, Common Platform, at IBM. "In order to address these issues, the Common Platform companies worked with Cadence engineers to deliver this 45-nm reference flow. The result is an innovative yield-aware solution with seamless implementation of power intent using CPF."