will be under system maintenance from Tuesday June 28, 6pm PT to Sunday July 3, 11pm PT. Login and registration will be disabled.


Cadence C-to-Silicon Compiler Named Hot Product of 2008 by EDN Magazine
Every December, EDN Magazine editors decide on the "Hot 100 Electronic Products" released that year. This year, the new Cadence® C-to-Silicon Compiler high-level synthesis solution made the list. For more than 15 years, ASIC designers have sought technology able to transform any C/C++ algorithm into functionally correct, optimized RTL. Cadence C-to-Silicon Compiler delivers on that goal, and now extends support to FPGA designers, boosting their productivity up to 10 times in creating and reusing system-on-chip (SoC) IP.

With C-to-Silicon Compiler, engineers take their designs from a high level of abstraction to a final SoC through an integrated implementation and verification flow. Two innovations make C-to-Silicon Compiler unique: Embedded Logic Synthesis (using Cadence Encounter RTL Compiler) to enable high-quality synthesis of control and datapath logic, and a powerful Behavior Structure Timing database to enable incremental/ECO synthesis (verified using Cadence Encounter Conformal ECO Designer). Originally focused on ASICs, the new release of C-to-Silicon Compiler delivers the same productivity and reuse benefits of high-level synthesis to IP block designers targeting Altera and Xilinx FPGAs.

These capabilities, along with C-to-Silicon Compiler's ability to maintain total separation between design functionality and constraints, enable automatic retargeting and reuse of IP to different applications. Consequently, engineering teams can reduce design costs up to 90% without sacrificing quality—both ASIC and FPGA designers will achieve equal or better area, timing, and power results compared to other current methods.

Press Release
From EDN Editors
Product Info
From the Community

Feature stories archive »