The Cadence® Allegro® and Cadence OrCAD® family of products for PCB design and IC packaging/SiP design provide automation, advanced co-design, and constraint-driven flows that speed product development—from concept and capture to manufacturing. The latest Allegro and OrCAD release (16.2) enhances these solutions with new capabilities that address current and future business-driven technology challenges, including miniaturization, shorter product lifecycles, increasing design speeds, and environmental concerns.
In the area of product miniaturization, significant improvements for designers using high-density interconnect (HDI) will be of particular value to customers in the high-end consumer and wireless handheld electronics market, as well as in the computing and networking segments where users are seeking a constraint-driven HDI design flow. "Cadence has excelled in constraint-driven PCB design flows for many years, but customers also increasingly demand an HDI capability," explains Steve Kamin, Group Director PCB and IC Packaging Product Marketing, Cadence Design Systems. "With the significant improvements in the latest release of our PCB and IC packaging technology, Cadence now offers both of these capabilities, and some of our customers already are seeing the benefits of our constraint-driven HDI design flow."
"Harris has worked closely with Cadence on improvements in Allegro," said Charlie Davies, Principal ECAE Application Engineer at Harris Government Communications Systems Division. "We are part of a small, diversified group of customers providing feedback to Cadence on improvements in Allegro 16.2. The biggest improvement in the Allegro 16.2 release has been in the area of designing PCBs using a build-up process with High-Density Interconnects. With the addition of capabilities for HDI, Allegro provides an excellent constraint-driven HDI design Flow. These advances along with other ease-of-use improvements will significantly improve our ability to execute our most difficult HDI design challenges, while reducing our design cycle time."
Enhancements such as these make 16.2 a very important release for PCB and IC package designers. For example, the HDI capability includes new features such as enhanced design rules for microvias and same-net elements, along with powerful automation-assisted interconnect and via pattern insertion. Manufacturing IP-driven wirebonding from Kulicke & Soffa and co-planar waveguide modeling further boost productivity and reduce manufacturing-driven ECOs. Shrinking Product Lifecycles
To deal more effectively with product lifecycle issues, the Allegro and OrCAD 16.2 release delivers features such as extended rule-driven assembly rule checking for IC packages, auto-intelligent step and repeat of complex placement patterns, and enhanced automation for PCB layout-driven RF design. It also enables IC package/SiP team-based design to reduce design cycle time and make resource usage more efficient.
Additionally, all Allegro and OrCAD products—from front-end design creation to signal integrity to back-end layout—have been enhanced in the 16.2 release. One new capability enables customers to integrate RF circuits on PCBs together with digital and analog circuits. The Allegro PCB RF Option achieves this with two major enhancements: a bi-directional interface with the Agilent ADS RF design environment, and a new layout-driven RF design capability that makes it easier to modify RF circuits. The layout-driven RF design capability in the Allegro PCB RF Option also allows users to add RF circuit elements—stripline or microstrip elements—and the system will automatically create RF schematic elements through a back-annotation process. This eliminates the need for RF designers to manually create RF schematics for changes made in the layout, shortening design cycle times and reducing the risk of introducing manual errors.
The proven Cadence constraint-driven PCB design flow also provides additional control of constraints that electrical engineers need in specifying their design intent. Engineers can now specify physical and spacing constraints on critical nets and embed those in the design. These constraints are required for signals such as those found in DDRx memory interfaces, where the engineer needs to specify line widths and spacing to manage impedance and shield critical signals from crosstalk.
Cadence OrCAD Capture further delivers improved capabilities for designing FPGAs into products. Users can easily import an FPGA’s pin assignment from FPGA vendor tools. It also creates split symbols, and allows users to control how the symbols are split. This makes it easier to integrate an FPGA into the PCB design. Should a user choose to make changes to the FPGA pin assignment, OrCAD Capture provides the capability to export an updated pin assignment to the FPGA vendor’s tool. With this release, it supports Altera and Xilinx formats for import and export. Future support for other vendors will be provided based on customer requests.
Users of the 16.2 release will also notice improvements to the Graphical User Interface and Use Models in Allegro PCB Editor as well as other Allegro and OrCAD products. Enhancements include a new application mode for placement in Allegro and OrCAD PCB Editors, improved snapping capabilities with many choices on RMB, and new font support and keyboard shortcuts in Allegro Design Entry HDL. Increasing Design Speeds/Streaming Data
As video data is being pervasively streamed throughout the Internet and wireless infrastructures, many products now require parallel memory interfaces (i.e. DDR3) running at speeds over a gigahertz and serial interfaces (i.e. PCI Express) transmitting 5 to 10 gigabits per second. The 16.2 release will help accelerate the development of these designs by enabling more accurate simulation and compliance testing of high frequency interfaces. Standard eye masks can now be easily incorporated into multi-bit simulations to insure that bit error rate requirements are met. New high frequency field solver technology is available to create S-parameter models for PCB structures and enhanced 3D field solver technology from preferred technology partner, Apache Design Solutions, can now be incorporated into the IC Package and SiP SI solutions to ensure accurate die to die modeling of high frequency interconnect. Modeling of advanced SerDes transceivers with the newly adopted IBIS-AMI standard now enables simulations with devices from different vendors at opposite ends of the serial link. This release includes a model development kit that can be used to develop IBIS 5.0 AMI compliant models. The new IBIS 5.0 standard is a result of Cadence, SerDes vendors, and other EDA companies coming together to enable accurate simulations of devices that are required for the latest serial link standards. Environmental Concerns/Green Design
With the increasing awareness of the need to develop products that help protect the Earth’s climate and conserve resources, the 16.2 release helps companies go green. Design teams can make their products more efficient using new capabilities such as IC package power delivery analysis (which includes an integrated power analysis flow that is supported by 3D extraction of signal, power, and ground signals). It also includes the ability to optimize package PDN impedance voltage while minimizing voltage ripple. These and other enhancements also help co-design teams to optimize low-power system designs.
From improved high-speed flows to enhanced ease of use across the range of products, users will find a number of ways that the newest release of the Allegro and OrCAD family of products improves productivity and helps to address today’s and tomorrow’s critical challenges.