Global Unichip and Cadence Strive for Energy Efficiency in Chip Design
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One of the industry’s top SoC design foundries, Global Unichip (GUC) helps customers around the world develop feature-rich electronic products with ultra-low-power design requirements.
Power consumption is GUC’s major concern when optimizing SoCs for system-level integration—especially for systems designed at advanced process nodes. GUC can address leakage and dynamic power issues with techniques such as power domain partitioning and dynamic voltage/frequency scaling.
But to really win customers’ confidence in achieving rigorous design specifications on a tight schedule, GUC requires a mature and comprehensive solution that ensures every design step is power domain–aware.
The Cadence® Low-Power Design Solution
, enabled by the Si2 Common Power Format (CPF), provides GUC with a complete system-to-silicon power-aware tool flow. CPF captures all power-related design intent, constraints, and functional requirements in a single file. It ensures that power intent is interpreted consistently, implemented correctly, and verified thoroughly at every design stage. The CPF-enabled tool flow is a key feature for GUC since it dramatically reduces the risk of specification misses and re-spins.
Find out how Global Unichip has been working with Cadence for five years to tape out more than 100 low-power designs.