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SMIC-Cadence Collaboration Delivers In-Design DFM Flow to Mutual Customers
Design-for-manufacturing (DFM) strategy has evolved from a “nice-to-have” into a “must-have.” Systematic variations due to lithography, such as timing glitches, thickness variations, and hotspots, are the greatest cause of electrical malfunctions and catastrophic chip failures. Especially at complex 45nm processes, engineering teams need a comprehensive DFM flow to prevent, predict, detect, and correct the effect of variations on design performance and yield.

The EDA360 ecosystem recognizes DFM as a crucial step in the IC design flow and encourages collaboration to bridge the lithography-manufacturing gap. The best DFM strategy not only tackles the productivity slump caused by systematic and electrical variations, but also addresses design-to-silicon flow issues that affect profitability. Recent collaboration between Cadence and SMIC highlights what can come of the EDA360 silicon realization infrastructure. In the following video, Semiconductor Manufacturing International Corporation (SMIC) describes their joint effort with Cadence in creating DFM-clean libraries and accurate IP, CMP, and litho models for their worldwide customer base.

SMIC is one of the industry’s leading semiconductor foundries and the largest, most advanced foundry in Mainland China, providing IC foundry and technology services from 0.35um to 45nm. SMIC leveraged Cadence DFM solutions to analyze the impact of process-induced stress on the electrical performance of their libraries and to automatically fix the affected transistors. SMIC also validated Cadence CMP and litho models and have made them available to all of their customers, who now benefit from a stable, predictable in-design DFM flow for custom and digital silicon realization.

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