Cadence Pattern-Matching Technologies Accelerate Full-Chip DFM Signoff at GLOBALFOUNDRIES
GLOBALFOUNDRIES provides technologies for advanced silicon manufacturing at 130nm down to 20nm. To guarantee high yield and manufacturability at advanced process nodes like 32/28nm, GLOBALFOUNDRIES needed to go beyond traditional design-rule checking (DRC) and develop a new set of incremental design-for-manufacturing (DFM) verification methodologies.

To that end, GLOBALFOUNDRIES collaborated with Cadence to pioneer pattern-matching—based DRC+ technology. DRC+ augments the traditional DRC flow with a library of yield detractors (2D shapes that are difficult or impossible to manufacture), as well as a set of recommended rules to automatically fix 2D shapes. With these capabilities, DRC+ speeds full-chip model-based DFM signoff by up to four orders of magnitude, driving faster turnaround times and first-pass—correct silicon.

At the heart of DRC+ lie two foundational Cadence technologies. Cadence Pattern Search and Match verifies physical layouts in production at 32nm and 28nm. Cadence Pattern Search and Classification identifies exact and inexact geometric similarities among different families of patterns.

In addition to superior pattern-matching verification speed, the Cadence implementation of DRC+ detects yield detractors early in the design flow and has been integrated into the Virtuoso custom/analog and Encounter digital flow.



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