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Xilinx Relies on Incisive Enterprise Simulator for Swift IP Design Testing
A top FPGA provider, Xilinx ensures its IP designs behave as intended by testing all relevant combinations of the parameter values that could affect any given design. However, exhaustive testing for all permutations of a parameter set – even with a modest number of parameter values – can introduce prohibitively long turnaround times.

To accelerate its development cycle, Xilinx uses Cadence Incisive Enterprise Simulator with Specman macros. The Cadence solution specifies which parameters need to be exhaustively generated (i.e., all the combinations of their values), and which fields can be simply randomized.

In addition to runtime improvements that save Xilinx 20% to 30% in simulation time, the Specman macro solution is flexible, easy to use, and effectively free as all Enterprise Simulator licenses include a Specman license.

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