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Cadence Digital/Mixed-Signal Solution Helps Texas Instruments Achieve Verification Results 300x Faster
The latest generation of the Texas Instruments (TI) MSP430 microcontroller is a complex mixed-signal design that operates in ultra low-power mode. With numerous analog and digital components interacting closely, and with each component having different power states, a fast and accurate verification solution was critical for TI to reach their quality goals on budget and on schedule.

TI had successfully adopted a digital-centric metric-driven verification methodology years earlier, but to extend this methodology into the mixed-signal domain, they needed more robust simulation capabilities to handle the MSP430’s complex modeling requirements. Cadence proposed that TI use the Incisive Enterprise Simulator Digital/Mixed-Signal (DMS) Option.

Modeling the analog components in traditional (pure-digital) Verilog could not provide the accuracy needed to verify the MSP430’s complex analog-to-digital and digital-to-analog interactions. For the DMS methodology to be effective, Cadence helped the TI team replace all analog components with real-value models (“wreal” models) using Verilog-AMS. A wreal model represents a truly-valued physical connection between structural entities and is therefore ideal to model analog voltages or current. And since the digital engine solves the wreal model descriptions, it eliminates the use of the analog solver during mixed-signal simulation to greatly increase simulation performance.

Before the Cadence DMS solution, TI engineers had to wait for all mandatory analog blocks to complete. They may have skipped a test and found the problem in the silicon, setting the project back by six months or more. Now the TI design team can start verification early, simulating an analog block with a real-number model.

“In one top-level mixed-signal simulation we determined that the Cadence DMS verification solution, with its ability to replace electrical components with their real-number model equivalents, provided 300x faster verification results than simulation at the transistor level with equivalent accuracy,” explains Roland Nerlich, Digital Design Engineer at TI.

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