Cadence Technology Enables Low-Power Design and Implementation of Complex Kinetis SoC
Freescale’s family of Kinetis SoCs comprise highly integrated low-power, mixed-signal 32-bit microcontrollers based on the ARM® Cortex™-M4 core. On a recent Kinetis project, Freescale engineers identified aggressive power targets in at least 10 different power modes. Adding to the challenge, the design had nearly 70% new content including thin-film storage Flash memory and 85 mixed-signal IP blocks.

Freescale collaborated with Cadence to achieve their power goals. Using the Cadence® Low-Power Solution and its advanced low-power design and implementation flow, Freescale ultimately reduced dynamic power consumption by 30% and static power consumption by 80% in the off-state.

    
The Cadence Low-Power Solution provides a comprehensive, interoperable, and proven methodology―from design planning to signoff. Using the Common Power Format (CPF), it leverages power intent pervasively and consistently to enable fully automated, correct-by-construction low-power implementation.

The Freescale team employed a number of low-power techniques, supported in several Cadence technologies, including:
  • Automated clock gating during synthesis and power-aware scan insertion ― Encounter® RTL Compiler
  • Automated optimization of multi-voltage libraries ― Encounter RTL Compiler and Encounter Digital Implementation System
  • Extended gate-length libraries ― Encounter Digital Implementation System
  • Power-aware simulation ― Incisive technology
  • Formal verification ― Conformal® Low Power


The design was a success and taped out within a few days of the original schedule. Freescale is now building on the success of the Kinetis SoC family and continues to use the Cadence Low- Power Solution widely in its design projects.

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