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Home > About Cadence > Newsroom > Cadence Articles > Cadence Announces New In-Circuit Acceleration Capability and Expanded Support for Accelerated VIP
Cadence Announces New In-Circuit Acceleration
Capability and Expanded Support for Accelerated VIP

To help customers streamline their verification process for complex systems and SoCs, and to speed the delivery of next-generation consumer and wireless electronics products, Cadence has expanded our System Development Suite and Verification IP (VIP) Catalog with new capabilities for acceleration and emulation.

The System Development Suite now supports in-circuit acceleration, based on the Verification Computing Platform (Palladium XP) and the Incisive Verification Platform. In-circuit acceleration delivers—in a single environment—speed, connectivity to real-world interfaces of our industry-leading in-circuit emulation technology, and the advanced debug capabilities of simulation acceleration.

Such enhancements to the Suite’s performance as a heterogeneous platform allow engineers to target various portions of their design using the different execution engines on an as-needed basis, and to find the optimal balance between system performance and accuracy.

With our VIP Catalog’s extended support for acceleration and emulation, users can smoothly transition from traditional simulation to acceleration and emulation, allowing them to verify complex systems and SoCs that are too large for RTL simulation.

System Development Suite
The System Development Suite is a set of four connected platforms designed to accelerate system integration and validation through simultaneous hardware/software development. Now with enhanced heterogeneous-platform support, the Suite delivers a single, unified system-level verification environment that is scalable and customizable.

Each of the four underlying platforms features new capabilities:
  • Virtual System Platform: open processor abstraction layers for unified multi-core software debug
  • Incisive Verification Platform: 10x faster low-power elaboration; early access to black-boxing
  • Palladium XP: CPF acceleration support for code and toggle coverage; dynamic power analysis in acceleration mode
  • Rapid Prototyping Platform: automatic memory re-mapping; external SRAM and DDR2 memory modeling with backdoor access
VIP Catalog
More than 500 customers worldwide use the Verification IP (VIP) Catalog to speed verification of 40+ interface protocols and 6,000+ memory models. Now facilitating the high-speed transfer of interface traffic through a design under test in Palladium XP, Cadence Accelerated VIP (AVIP) enables engineering teams to dramatically boost the verification performance of designs at any integration level: IP, subsystem, SoC, and system.

Cadence AVIP is compatible with the Universal Verification Methodology (UVM) and is available immediately for the following standards: ARM® AMBA® AXI™ 3.0/4.0, AMBA 4 ACE™ and ACE Lite; PCI Express 2.0/3.0; USB 3.0; Ethernet 10G; SATA 3; and HDMI 1.4.

"Using In-Circuit Acceleration, we’ve enabled a new paradigm of system-level debug productivity while maintaining full In-Circuit Emulation performance. We have reduced the time to closure on difficult, long running workloads, which enables us to increase our hardware and software coverage while reducing the overall test plan execution time."
Alex Starr
Emulation Architect, Advanced Micro Devices
"The evolution that Cadence took with System Development Suite is impressive. We are now exploring new ways to co-execute the Palladium system with virtualized models and debug engines."
Narendra Konda
Director of Engineering, NVIDIA

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