Custom designers benefit from greater performance, capacity, and productivity with the latest Virtuoso release
For many customers, custom design is the most profitable part of the business—and the most challenging. Complicating matters further is the breadth of what “custom design” means. Is it analog or custom digital? Mixed signal or RF? Is it traditional 180/130nm process nodes or is it on the bleeding edge of 32/28nm? For Cadence and its customers, it’s all of the above. And that is why the world’s leading semiconductor manufacturers rely on comprehensive Cadence® Virtuoso® platform
to develop the most advanced custom ICs and SoCs.
Virtuoso analog implementation technology is the industry leader in its market segment. As such, it is a priority at Cadence to continually enhance the Virtuoso suite and deliver the sophisticated technology and usability levels our customers ask for. The new Virtuoso IC 6.1.4 release offers greater capacity, performance, and usability to reduce overall design time while ensuring high-quality production of analog/mixed-signal ICs and SoCs. With an array of new features and functionalities, custom designers will have access to cutting-edge technology that allows them to explore the “What If’ so critical to high-quality design creation, while avoiding the “What Now” pitfalls that stand in the way of profitable design.
“We recently reviewed the custom design technology from multiple EDA providers and felt the Cadence Virtuoso suite gives us the most complete design flow, efficiently connecting one design stage to another,” said Paul Browne, vice president of Engineering at Vitesse, a leading provider of advanced IC solutions for carrier and enterprise networks. “We expect to reduce our overall design time using Virtuoso technology, and we expect additional benefits as we adopt some of the more advanced capabilities of this new release.”
“Our new Virtuoso release offers enhancements that will translate into significant time and quality benefits for users of our leading custom IC and mixed-signal technology,” said Cadence CMO John Bruggeman. “There is a reason Virtuoso technology remains the leader in its space and, as our customers are discovering, this latest release will only further advance the Virtuoso brand.”
Performance and Capacity
The new Virtuoso release has been extended to work efficiently at advanced nodes down to 28 nanometers. And it now supports 64-bit processing for improved capacity and performance across the entire platform. Integrating the Virtuoso Space-Based Router
into the Virtuoso Layout Suite
brings the power of a 1 million net-capable router to the desk of every layout engineer. Interactive wire editing and full-chip automatic finish routing now share the same algorithms, providing a seamless flow for higher design quality, from IP module creation though full-chip signoff. The 6.1.4 release extends the Cadence Express Pcells capability to support multiple-user sites. Now customers can use their vast libraries of SKILL parameterized cells (Pcells) anywhere and see performance improvement up to 8 times. Cadence has improved the analog display technology to handle multi-gigabyte waveform files more efficiently, removing the 2-gigabyte limit on waveform databases to account for today’s larger, more complex designs. Finally, performance has been boosted for underlying design-rule engines in the Virtuoso Layout Suite.
New display capabilities in Virtuoso Analog Design Environment
XL can now produce more, and better, datasheets. The Virtuoso Analog Design Environment’s ability to analyze multiple tests simultaneously, including those across corner and statistical variations, helps engineers pick the best circuit design directions early in the design cycle, and verify those choices efficiently post-implementation.
The Cadence design constraints methodology—which helps engineers reduce layout and design refinement times by as much as 20 percent—has been enhanced to make it easier to add design constraints. In addition, there are new design constraints specifically geared to address sub-45-nanometer design yield challenges.
The ability to measure designer productivity is tricky and, in the past, has been very subjective. While it is impossible to learn about some aspects of usage via an interview process, this is both time-consuming and imprecise—most users only remember the “big things” they did and the minor details are lost. These subtleties are often the key to understanding and improving productivity with custom design tools.
Cadence took a novel approach to enhancing productivity within the Virtuoso platform: the new 6.1.4 release saves information in a format that can be “mined” with analysis tools. With the ability to analyze exactly what the designer did, how long it took, and what the end result was, customers can determine where productivity declines during their design cycle. So that the designer is not disturbed, this productivity data is collected non-intrusively and the analysis is performed as a post-processing step. This insight into productivity not only helps customers streamline their design cycles, but also provides Cadence with valuable usage information to constantly improve Virtuoso technology for our customers around the globe. Feature stories archive »