Cadence has announced the extension of its broad portfolio of verification IP (VIP), delivering a one-stop shop for early IP and SoC verification and hardware/software integration. The new offering combines mature, metric-driven Cadence® VIP with Denali memory models, support for all major third-party simulators, expanded support for mainstream and emerging protocols, and new use models such as Accelerated VIP for system validation.
Available now, this robust solution can be used across silicon, SoC, and system development to reduce verification risk, stay on budget, and get the most complex devices into volume production faster than ever before.
Expanded protocol support for early silicon IP and SoC verification
High-quality Silicon Realization requires fast and accurate verification that IP blocks comply with standard interface specifications. Cadence delivers a stable, mature solution that performs extensive protocol checks, tests, and coverage reports, allowing customers to create silicon hardware that complies with the latest protocol versions.
What was already the industry’s broadest portfolio is now even bigger with support for more than 30 protocols, both mainstream and emerging. The new Cadence VIP Catalog
enables early delivery of VIP for the latest emerging protocols in the ARM® AMBA® 4 family and the MIPI family (M-PHY, DigRF, UniPro). With the new offering Cadence sustains its leadership in supporting other newer protocols such as PCI Express Gen3, SuperSpeed USB, Ethernet 40/100G, and SLIMbus.
“As a technology leader and global IP supplier, ARM sees firsthand that the complexity involved with designing today’s SoCs and systems is matched only by the complexity entailed with verifying them,” said Joe Convey, director of design enablement, ARM. “Our customers create the world’s most advanced products and depend on the latest verification technology to reduce risk and speed time to market. With its high-quality verification IP that spans leading protocols, such as the newly released AMBA 4 specification for efficient SoC and FPGA designs, Cadence delivers the breadth and depth engineers need to validate a wide scope of designs, from the mainstream to the most advanced technology available.”
“The MIPI Alliance of over 200 member companies develops interface specifications that drive consistency in processor and peripheral interfaces, promoting reuse and compatibility in mobile devices,” explains Joel Huloux, Chairman of the MIPI Alliance. “As a longtime contributing member, Cadence has helped advance the evolution of several MIPI protocols and their rapid adoption by IP and SoC companies.”
Al Yanes, PCI-SIG President and Chairman, adds, “PCI-SIG, with over 800 member companies, is the industry organization responsible for development and management of the PCI Express specification. We are delighted that Cadence continues to facilitate rapid industry adoption of the PCI Express 3.0 architecture via its family of Verification IP products.”
For SoC Realization, developers can use the new Cadence VIP portfolio for full-chip verification, validating that the entire subsystem IP is integrated and operating correctly. The addition of proven Denali technology offers developers a consistent testbench interface to improve productivity, and an expanded memory model portfolio (DDR4, LRDIMM, Flash ONFI 3.0, and more) to help verify interconnect, control, and data flow throughout the entire SoC.
With support for multiple protocols and memories in the same simulation, SoC verification is more flexible. A new packaging strategy aligns cost with protocol complexity, removing the cost barrier to high-quality SoC verification. And, the Universal Verification Methodology (UVM) is compatible with the entire portfolio.
An open environment and new use models for HW/SW integration and system validation
Nearly all design and verification teams rely on multiple simulators, making it unrealistic for customers to transition to a Cadence-only simulation model. The new Cadence VIP Catalog supports all major third-party simulators, including VCS and Questa. Such simulation technology gives customers the flexibility to deploy Cadence VIP on top of their existing environment.
New use models enable hardware/software integration for full system validation. Cadence Accelerated VIP
links HW/SW verification with traditional RTL verification. To enable software-driven verification, Cadence is extending the solution to provide a programmer’s view of system verification to test drivers and SoC interfaces concurrently.
“Effective verification continues to dictate project schedules and costs, with companies expending tremendous efforts on IP and SoC verification and on ensuring system correctness,” summarizes Nimish Modi, Senior Vice President of the System and SoC Realization Group at Cadence. “This comprehensive set of Cadence VIP and memory models, coupled with enhanced features and capabilities, help speed verification for IP, SoCs, and systems, leaving design teams more time to focus on creating unique, differentiated content.”
Cadence VIP experts Susan Peterson and Sean O’Kane discuss the benefits of the new Cadence VIP Catalog