As design complexity has grown with each advancing node, verification flows have become fractured and inefficient, with separate niche flows created to address such challenges as mixed signal, low power, and formal analysis. At 90nm, you may have to sell 400K more chips to cover the cost of a 10% overrun in your verification program (source: IBS 2010).
To help manage this risk and boost verification productivity, Cadence has just announced new advancements for ASIC and FPGA designers. With the release of Incisive 10.2 technology, Cadence is providing more than 600 new capabilities that expand the scope of its metric-driven verification
(MDV) solution. Coupled with full support for the emerging Accellera Universal Verification Methodology (UVM) 1.0 industry standard, the latest Incisive technology will help engineers achieve faster, more comprehensive verification closure with a holistic approach to Silicon Realization
, which focuses on unified design and verification intent, abstraction, and convergence.
With the new release of Incisive technology, verification engineers can merge coverage data from formal analysis and simulation engines within a unified verification plan. Additional capabilities that expand the scope of the verification intent include support for enhanced low-power corruption and isolation simulation, as well as automated guidance for handling inconclusive results from formal analysis.
Earlier bug detection is enabled through additional abstraction capability, including support for the UVM 1.0 standard for testbench verification. Cadence is delivering additional support based on the UVM, including low-power
methodologies. Features such as validation of digital/mixed-signal models against detailed transistor models, debug support for macros and finite state machines, and reference implementations of these methodologies in the Incisive Verification Kit
will boost productivity for project teams.
In addition, improved engine performance will enable faster convergence of the verification process to the verification plan. For customers running thousands of regression tests, the new Incisive Specman Advanced Option provides reseeding of e
-based tests, multi-core e
code compilation, and the ability to debug mixed interpreted and compiled code, thereby improving overall productivity by 1.4x. Other capabilities to speed convergence include support
for multi-core formal analysis and 1.3x faster SystemVerilog testbench simulations.
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