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Home > About Cadence > Newsroom > Cadence Articles > Cadence to Premier Udacity MOOCs Course on Functional Hardware Verification at CDNLive Silicon Valley, March 12
Enroll in New Functional Hardware Verification Course Today

Cadence is pleased to premier a new massive open online course (MOOC), CS348 Functional Hardware Verification, at Cadence CDNLive Silicon Valley on Tuesday, March 12. The MOOC is part of a collaboration that Cadence and several other technology companies announced last fall with Udacity.

Enroll in the Cadence Functional Hardware Verification class today!

What Will I Learn?
In this class, you will learn how to program verification efficiently, to understand and leverage automation such as constrained random test generation, and to improve code reuse leveraging a standardized methodology. You will understand how to think like a verification engineer, and gain insights into software development aspects you need to know to ensure chips are working as expected.

The full self-paced, nine-unit course promises a high level of engagement and interaction, and will include presentations from several of the world’s most distinguished engineers. You will also have an opportunity to test your knowledge by writing snippets of real verification code. In real time, a cloud server will parse your input and return feedback until the code fragment is correct.

Course Agenda
1. Introduction to Hardware Verification
2. Basic Stimulus Modeling and Generation
3. Interfacing to the Hardware Model
4. Monitoring and Functional Coverage
5. Checking
6. Aspect-oriented Programming
7. Reuse Methodology
8. Debugging
9. Conclusion and Exam

After you’ve successfully completed all of the course components, including the final exam, you will be presented with an Udacity certificate that summarizes your performance.

What Should I Know Before Getting Started?
To be successful in this class, you should have programming experience including object-oriented programming, data, and control structures.

Course Instructors

Axel Scherer
Axel Scherer is a senior engineer and manager with over 10 years of experience building new markets and innovating technical products. Currently, Axel is leading a team for Testbenches and Verification Methodologies in the Functional Verification R&D group at Cadence Design Systems, a leading global electronic design automation company. Axel's work centers on advanced verification on various technologies spanning formal equivalence checking, model checking, assertion-based verification, and test bench simulation. He is a passionate and innovative leader with a proven track record of motivating and enabling global teams to succeed.

Hannes Fröhlich
Hannes Fröhlich is a member of the Product Expert Team in the Functional Verification R&D group of Cadence Design Systems, a leading global electronic design automation company. Hannes' primary focus area is the Specman/e and UVM multi-language solution. He has over 10 years of verification experience spanning from an AE to AE Manager to Solutions Architect. He has been involved with assisting customers implementing Specman/e technology around the globe, and his expertise has enabled hundreds of successful projects.

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