will be under system maintenance from Tuesday June 28, 6pm PT to Sunday July 3, 11pm PT. Login and registration will be disabled.
Home > About Cadence > Newsroom > Cadence Articles > Cadence DRAM IP Paper Wins TSMC Customers' Choice Award
Customers Recognize the Value of Cadence Design IP

Cadence received the prestigious “Customers’ Choice Award” for our paper on DRAM IP at TSMC’s recent Open Innovation Platform Ecosystem Forum. Entitled “Using Latest-Generation DDR4, LPDDR3, and Wide-I/O DRAM Devices with Chips in TSMC’s Advanced 28nm and 20nm Processes,” the paper focuses on current and emerging trends in high-speed memory interfaces—and the design IP required to enable them.

L-R Jason Chen (Cadence), Diana Tai (TSMC), Martin Lund (Cadence), Tom Quan (TSMC), John Murphy (Cadence), Rob Raghavan (Cadence)

Dynamic random access memory (DRAM) is the most popular form of memory because it offers lower cost per bit while also providing longer access time. Bandwidth requirements for DRAM are growing exponentially. Much progress has been made on standards for new high-speed interfaces like DDR4, LPDDR3, and Wide-I/O, and mainstream adoption is expected by 2015. While mainstream adoption is not expected until 2015, Cadence and TSMC are working together to enable early adoption at advanced nodes.

At the Ecosystem Forum, Cadence presented the latest results of this ongoing collaboration, highlighting our memory controller and hard physical layer (PHY) IP used to produce test chips in TSMC processes. Attendees learned how to:
  • Reach high speeds like DDR4-2400 (2.4Gbit per pin) in TSMC 28HP and 28HPM
  • Reach low-power goals using LPDDR2 and LPDDR3 in TSMC 28HPM
  • Build DDR interfaces in TSMC 20SOC
  • Use TSMC CoWoS technology to connect to Wide I/O DRAM
  • Leverage advanced capabilities in the areas of 3D-IC design and hybrid memory cubes
The award-winning paper also touched on the benefits of Cadence Design IP for high-speed memory interfaces:
  • High-performance architecture: get more bandwidth with less power consumption
  • Configurability: differentiate your chip while reducing design-in time
  • High-quality memory controllers and proven PHYs: reduce your risk
The “Customers’ Choice Award” for the Cadence DRAM IP paper marks the second year in a row that attendees at the TSMC event selected Cadence for the honor.

Sign in to receive Using Latest-Generation DDR4, LPDDR3 and Wide-IO DRAM Devices with Chips in TSMC’s Advanced 28nm and 20nm Processes paper.

“The Customers’ Choice Award acknowledges the value of the contributions Cadence is making to bring new DRAM technology to market faster. Working closely with TSMC and our customers, we have developed the IP and technology that enables early customer adoption.”
Martin Lund
Senior Vice President, R&D, SoC Realization Group, Cadence
“Cadence is helping our customers bring their next-generation technology to market. Innovation in important areas like memory interface IP can have a significant impact on our customers’ success, and this award is a reflection of that.”
Suk Lee
Senior Director of Design Infrastructure Marketing, TSMC

Press release: Solution:
Feature stories archive »