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Home > About Cadence > Newsroom > Cadence Articles > Cadence and TSMC Extend Collaboration to 20nm and to Wide I/O on CoWos
Partnership Critical to 20nm Success and 3D-IC Adoption

Cadence and TSMC have been collaborating closely for more than 10 years to bring the most cutting-edge design tools and techniques into mainstream use. Our collaboration makes it possible for mutual customers to adopt advanced nodes, ultra-low-power flows, emerging protocols, and advanced packaging approaches—predictably and profitably.

As a Platinum Sponsor of this year’s TSMC Open Innovation Platform (OIP) Forum, Cadence is pleased to announce that our latest 20-nanometer and 3D-aware technologies are qualified for two TSMC Reference Flows.

Specifically, new 20nm capabilities in the Cadence Virtuoso and Encounter platforms have been certified for the TSMC 20nm Reference Flow. This ensures that mutual customers have immediate and comprehensive support for design, implementation, and signoff on custom/analog, mixed-signal, and digital designs using the 20nm process.

Furthermore, Cadence 3D-IC technologies (including our IP for Wide I/O) have been validated for the TSMC CoWos Reference Flow. This provides mutual customers with a 3D-aware design flow and a high-bandwidth memory interface, allowing them to adopt an advanced packaging approach and develop the highest-performance, lowest-power mobile devices.

20nm Enablement
With its unique challenges in yield, manufacturing, and cost, the 20nm node requires a new approach to make the ecosystem ready for production designs. Cadence and TSMC have been collaborating on double-patterning technology (DPT), complete signoff, and extended SKILL support—all of which are critical to success at 20nm. A qualified SKILL process design kit (PDK) for the 20nm process, and TSMC rule decks for the Cadence Physical Verification System, are available now.

Virtuoso and Encounter technologies certified for TSMC’s 20nm process include:
  • Virtuoso 20nm constraints in the industry-standard OpenAccess database
  • The new Integrated Physical Verification System, an in-design technology embedded within the Virtuoso platform
  • Encounter 20nm rules
  • FlexColor DPT for correct-by-construction placement and routing
  • GigaOpt engine for better quality of results and shorter turnaround time
  • Multi-flow support for color encoding and DPT corners extraction
  • 20nm double patterning and incremental DRC correction
  • 20nm models for hotspot analysis and repair

3D-IC Enablement
Three-dimensional IC (3D-IC) design combines custom and digital dies on the same stack, driving more advanced packaging techniques and bringing benefits to system-level performance, power, and form factor.

To make 3D-IC design a more viable and cost-effective option, Cadence and TSMC have collaborated to deliver the foundry segment’s first silicon-validated reference flow enabling multiple die integration.

TSMC has validated Cadence 3D-IC technology for its chip-on-wafer-on-substrate (CoWos) Reference Flow, leveraging the Wide I/O standard for its high-bandwidth and low-power advantages. TSMC developed a CoWoS test vehicle that includes an SoC using Cadence memory controller and PHY IP for Wide I/O.

Using CoWos technology and Cadence Design IP for Wide I/O, the SoC achieved a peak data rate of more than 100-Gigabits per second.

In addition to Wide I/O IP, validated 3D-IC technologies from Cadence include:
  • Automatic support for CoWoS combo bump cells in Encounter Digital Implementation System, QRC Extraction, and Physical Verification System
  • Cadence system-in-package (SiP) products
  • Recently acquired Sigrity technologies for power-aware chip/package/board signal integrity analysis that spans planning through implementation, test, analysis, and verification

“Our collaboration with Cadence covered complete mixed-signal and digital flows to ensure that the requirements for double patterning are implemented and fully tested. This will help our mutual customers achieve working chips as quickly as possible as they take advantage of this new process node.”
Dr. Cliff Hou
VP, Design and Technology Platform, TSMC
“We have been working closely with TSMC to develop comprehensive solutions to the challenges of 20nm design. Our TSMC-certified Virtuoso and Encounter 20nm technologies are uniquely integrated to deliver a unified flow that addresses the most challenging low-power mixed-signal chips.”
Dr. Chi-Ping Hsu
Sr. VP, R&D, Silicon Realization, Cadence
“TSMC continues to work closely with Cadence to bring 3D-IC to the industry. We have invested three years with Open Innovation Platform ecosystem partners to prepare the CoWoS design flow for production, and now we’re ready to enable customers’ 3D-IC designs with TSMC CoWoS technology.”
Suk Lee
Sr. Director, Design Infrastructure Marketing, TSMC
“The Cadence 3D-IC Solution enables the next generation of high-performance mobile devices, offering significant benefits in system performance and power efficiency. Our continued work with TSMC on the CoWoS process ensures that the infrastructure is in place to support this important emerging technology.”
Dr. Chi-Ping Hsu
Sr. VP, R&D, Silicon Realization, Cadence


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