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Home > About Cadence > Newsroom > Cadence Articles > TripleCheck IP Validator: A Third-Generation Solution for the Next Generation of SoC Realization
TripleCheck IP Validator: A Third-Generation Solution
for the Next Generation of SoC Realization

High-speed interconnect and cache-coherent system-on-chip fabrics make standard interfaces increasingly difficult to verify. TripleCheck IP Validator, the latest addition to the Cadence Verification IP (VIP) Catalog, greatly simplifies and accelerates compliance testing of interface IP. Built on previous generations of Cadence compliance solutions (PureSuite and the Compliance Management System), TripleCheck combines the three most critical components of verification in a single, easy-to-use environment: a test suite, coverage model, and verification plan.

Test suite
TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains both directed tests (quick checks for protocol compliance) and constrained-random tests (exhaustive checks for hidden corner-case bugs). TripleCheck tests work with all major logic simulators, and integrate with Incisive Enterprise Manager to enable bucket analysis of coverage and test profiling to eliminate unproductive test sequences.

Coverage models
TripleCheck coverage models support both SystemVerilog and e verification languages. These pre-defined coverage models capture all appropriate data to track and measure verification progress. Open and documented, the models can be extended with application-specific coverage definitions.

A Snapshot of TripleCheck IP Validator

Verification plans
TripleCheck provides a verification plan (vPlan) that mirrors the protocol specification. All requirements in the protocol specification are listed in the vPlan and organized into the same hierarchy as the specification. The vPlan is linked to the coverage model so that coverage data captured during simulation is automatically mapped against the plan. The vPlan also displays progress toward verification closure.

“Feedback from hundreds of users over several years was used to shape TripleCheck,” said Erik Panu, Vice President of R&D for Verification IP in the Software and System Realization Group at Cadence. “They wanted the extensive directed tests that PureSuite provided, plus the constrained-random testing approach of the CMS and its innovative vPlan…all based on the Universal Verification Methodology.”

TripleCheck IP Validator is immediately available for PCI Express Gen 3.

"Wipro has been consistently enabling semiconductor companies reduce verification time and increase coverage parameters through its next generation frameworks and market proven end-to-end verification services. Our partnership with Cadence has played an instrumental role in fulfilling the IP verification needs of our customers. We chose PCIe Gen3 VIP along with TripleCheck by Cadence to achieve a comprehensive solution that gives us the fastest path to IP verification closure."
A. Vasudevan, Vice President – Semiconductor and Systems, Wipro
"PCI-SIG® is the industry-leading organization responsible for development and management of PCI Express specifications. We are delighted that Cadence continues to advance the PCI Express 3.0 specification with their innovative verification IP products and methodologies."
Al Yanes, President and Chairman, PCI-SIG

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