Home > About Cadence > Newsroom > Cadence Articles > Sunplus Technology Adopts Cadence Transaction-Level Modeling Flow for Faster System Development Time
Open, Connected, and Scalable Flow for Faster, More Cost-Efficient System Development

Sunplus Technology designs multimedia ICs and SoCs for integration into DVD players, LCD and high-definition TVs, and set-top-boxes. To accelerate their schedule for their latest multimedia SoC design, Sunplus required superior modeling and simulation capabilities. They selected the Cadence® transaction-level modeling (TLM) flow with C-to-Silicon Compiler for its ability to generate high-quality results, quickly and predictably, and to control development costs.

Cadence C-to-Silicon Compiler delivers high-level synthesis. By deploying it with TLM, the Sunplus engineering team can design and verify their chips at a much higher level of abstraction. This allows them to explore more architectural options and more quickly re-target IP to optimize performance, power, and cost considerations.

“C-to-Silicon Compiler, as part of a TLM flow, helps our engineering teams optimize their designs early in the design cycle, including power characteristics,” said Cheng-Yuh Wu, Director of the Sunplus DVD IC Design Division I. “Perhaps most important, we can use System C, a more abstract language than traditional Verilog/VHDL, to do our design. This translates into shorter development time for complex designs, with higher IP reuse for subsequent end products.”

The Cadence TLM flow provides a connected path from system development down to silicon realization. It is also scalable, which boosts verification productivity and enables more IP reuse. Additionally, the TLM flow is open, with C-to-Silicon Compiler reading-in designs described in the IEEE 1666 SystemC standard.



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