Thriving in today’s electronics industry forces chip makers to squeeze all the electrical, physical, and functional requirements of incredibly complex designs into the tightest timeframes and budgets. Engineers need to work on all three axes simultaneously, and they require constant, real-time, and automatic communication among all domains.
But traditional EDA uses a “silo” approach to product development, in which point tools perform individual design tasks in isolation. Such a sequential, disjointed flow poses serious challenges to productivity, predictability, and—ultimately—profitability. At 130nm, the likelihood of hitting performance targets is 96%. At 40nm it drops to 71%. And at 22nm it will drop to 33%. An End-to-End, Deterministic Flow
Cadence is taking a new approach to silicon realization with an end-to-end, deterministic flow that concurrently optimizes functionality, electrical specifications, and physical requirements. This holistic approach to silicon design, verification, and implementation hinges on three critical requirements:
- Consistent representation of design and verification intent
- Accurate models and higher levels of abstraction
- Convergence of late-stage design/manufacturing data into the early phases of design
Only a design flow that meets all three of these requirements can tackle today’s most pressing customer challenges.
“Cadence R&D teams have been focused on building tools that meet these requirements of unified design intent, design abstraction, and design convergence, and our future product releases will continue to deliver on these core elements,” said John Bruggeman, Chief Marketing Officer at Cadence. “Ultimately, we expect to offer a number of seamless end-to-end design flows with built-in efficiencies that will give customers a meaningful market advantage.” Intent, Abstraction, and Convergence
Design intent is a uniform representation of specifications—timing, power, etc.—that can be applied consistently throughout the flow. Cadence developed the Common Power Format (CPF), now available as an industry standard. Cadence technology also supports common physical and electrical constraints between digital and analog environments, as well as metric-driven verification.
Design abstraction is the process of generating, validating, and integrating accurate, higher-level views of complex design data that capture essential elements at the right time. Cadence strongly advocates transaction-level modeling (TLM) in the digital realm. This approach reduces coding (and therefore bugs), speeds verification, and employs high-level synthesis to try a number of potential micro-architectures. Other abstraction capabilities supported by Cadence include wreal modeling, early architectural exploration and floorplanning, and low-power IP macro-modeling.
Design convergence is the ability to comprehend late-stage data early in the flow to optimize design tradeoffs. Convergence, when coupled with intent and abstraction, enables both a more deterministic top-down and bottom up approach to silicon realization. Cadence offers capabilities for hotspot identification; multi-objective, concurrent, physically/electrically-aware optimization; IC/package device optimization, and concurrent chip and package power modeling.
By focusing on design intent, abstraction and convergence, Cadence is carving a path that provides the tools and visibility engineers need to prevent silicon failures, push forward to more advanced process nodes, and stay competitive in the marketplace.
Feature stories archive »