Tempus Delivers Breakthrough Performance in Timing Signoff and Closure
Cadence has unveiled the Tempus Timing Signoff Solution, a new static timing analysis and closure tool that can help you move chips to fabrication faster than ever. Delivering performance that is up to 10X faster than that of competing products, the Tempus solution eliminates the signoff bottleneck, enabling you to meet your power, performance, and time-to-market goals.
The Tempus solution can handle designs with hundreds of millions of cell instances, without any compromises to accuracy. The solution has achieved timing closure in days on a design that would have needed up to four weeks with competitive products.
TSMC has certified the Tempus Timing Signoff Solution for 20nm designs. As such, the solution has passed TSMC’s rigorous tool certification process, enabling you to achieve the accuracy needed for advanced technologies.
"Certification is an integral part of TSMC’s overall design ecosystem. Cadence Tempus timing signoff tools are ready to address the design challenges of future TSMC process nodes. We worked closely with Cadence so Tempus could pass our acceptance criteria, and we look forward to teaming with them on future technologies."
Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division
Feature stories archive »